CP80C88Z Просмотр технического описания (PDF) - Intersil

Номер в каталоге

Компоненты Описание

Список матч

CP80C88Z

CMOS 8-/16-Bit Microprocessor

Intersil 

80C88

only. DT/R, IO/M and SS0 provide the complete bus status

in minimum mode.

• IO/M has been inverted to be compatible with the 8085

bus structure.

• ALE is delayed by one clock cycle in the minimum mode

when entering HALT, to allow the status to be latched with

ALE.

CLK

T1

T2

T3

T4

80C88

QS1, QS0

S2, S1, S0

A19/S6 - A16/S3

ALE

A19 - A16

S6 - S3

80C88

RDY 82C84

READY 80C88

AD7 - AD0 DATA OUT

80C88

A15 - A8

RD

DT/R

A7-A0

DATA IN

A15 - A8

80C88 MRDC

DEN

FIGURE 8. MEDIUM COMPLEXITY SYSTEM TIMING

15

FN2949.4

February 22, 2008

Share Link: