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IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

IMSA110

Figure 2 : Synchronous Functions of the IMSA110

PSRIN

1D

Programmable PSRC

shift register

D

D

0 to 1120 stages

1

1

2

8

8

CR1c coefficient registers 7 x 8 bits

CR0c coefficient registers 7 x 8 bits

D

3

X

X

1

D

X

X

1

1

1

D

D

D

22

D

Programmable PSRB

shift register

D

D

0 to 1120 stages

1

1

2

8

CR1b coefficient registers 7 x 8 bits

CR0b coefficient registers 7 x 8 bits

D

3

X

X

1

D

X

X

1

1

1

D

D

D

22

D

Programmable PSRA

shift register

D

D

D

0 to 1120 stages

1

1

2

3

8

MUX

1D

PSROUT

1

2

D

CIN

cascade input

CR1a coefficient registers 7 x 8 bits

CR0a coefficient registers 7 x 8 bits

X

X

1

D

X

1

1

D

D

22

D

13

Backend processing unit

including cascade data path,

normalization, saturation units and

data transformation look up tables

(see Figure 4 for detail)

X

1

D

22

D

5

1

2

COUT

cascade output

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