RS5C372A Просмотр технического описания (PDF) - RICOH Co.,Ltd.

Номер в каталоге

Компоненты Описание

Список матч

RS5C372A

I2C bus SERIAL INTERFACE REAL-TIME CLOCK ICs

RICOH Co.,Ltd. 

RS5C372A/B

2.2-2 ADJ

ADJ

0

1

±30 Second Adjust Bit

Ordinary operation

Second digit adjustment

Description

· The following operations are performed by setting the second ADJ bit to 1.

1) For second digits ranging from “00” to “29” seconds:

Time counters smaller than seconds are reset and second digits are set to “00”.

2) For second digits ranging from “30” to “59” seconds:

Time counters smaller than seconds are reset and second digits are set to “00”. Minute digits are incremented

by 1.

· Second digits are adjusted within 122µs (within 125µs: when 32.000kHz crystal is used) from writing operation to

ADJ.

· The ADJ bit is for write only and allows no read operation.

2.2-3 XSTP

Oscillator Halt Sensing Bit

XSTP

0

Ordinary oscillation

1

Oscillator halt sensing

Description

(Default)

The XSTP bit senses the oscillator halt.

· When oscillation is halted after initial power on from 0V or drop in supply voltage the bit is set to “1” and which

remains to be “1” after it is restarted. This bit may be used to judge validity of clock and calendar count data after

power on or supply voltage drop.

· When this bit is set to “1”, XSL, F6 to F0, CT2, CT1, CT0, AALE, BALE, SL2, SL1, CLEN and TEST bits are reset to

“0”. INTRA(INTR)* will stop output and the INTRB(32KOUT)* will output 32kHz clock pulses.

· The XSTP bit is set to “0” by setting the control register 2 (address Fh) during ordinary oscillation.

*) INTRA and INTRB for the RS5C372A, INTR and 32KOUT for the RS5C372B.

2.2-4 CLEN

32-kHz Clock Output Bit

CLEN

0

32-kHz clock output enabled

1

32-kHz clock output disabled

Description

(Default)

By setting this bit to “0”, output of clock pulses of the same frequency as the crystal oscillator is enabled.

19

Share Link: