SBPH400-3 Просмотр технического описания (PDF) - STMicroelectronics
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SBPH400-3 Datasheet PDF : 43 Pages
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SBPH400-3
decoder. Advanced logic is used to ensure reception of the Data and Strobe signals at speeds
of up to 400 MHz.
2.2 Connect detect and bias
A low current connect detect circuit is used to detect a physical connection. A current, applied
to the TPA pair and sensed via a local Schmitt trigger, will indicate a disconnected state unless
there is a physical connection to ground via the 5K resistor connected to the TPB pair at the
far end. Note that this does not require the far end to be powered. This mechanism operates
only when the port is not generating TpBias.
In order to implement the cable detection, suspend/resume and speed signalling functions, a
common mode bias voltage has to be provided to the TPA pair. A separate TpBias pin is
provided for each port, which should be connected to the TPA pair via a pair of 55 Ohm
resistors, as shown in Figure 2.1. The use of a separate pin for each port avoids problems of
possible interference between the common mode signalling on each port, or possible mis-
detection of a disconnect.
A single external resistor should be provided between pins R0 and R1 in order to set the
internal operating and the cable driver output currents. A low TCR 3KΩ ±1% resistor should
be used.
2.3 Configuration pins
The SBPH400 provides six configuration pins which may be hard wired high or low, or may be
directly controlled from a link layer device. Four of the pins are used to initialize registers which
control configuration status bits in the self identification packet.
The PC[0:2] pins provide the power reset value for the power class register, which is reported
in the Self_ID packet in the pwr field.
The CMC pin provides the power reset value for the C register, with is reported in the Self_ID
packet in the C field to indicate if the node is a contender for the bus or isochronous resource
manager.
The LACT pin is used to initialize the value of the Link_active register on power reset. If set to
zero, this allows the node to appear as having an inactive link (the L field in the Self-ID packet
will be zero) until application software sets the Link_active bit to 1.
The PDISABLE pin is used to initialize all ports as disabled on power reset. This satisfies the
OHCI requirement, and allows software to be initialized before the device starts to participate
on power-on as a new device on the bus.
The ISO pin is used on power reset to determine the operating mode of the PHY/Link interface
(DC coupled or using a DC isolation barrier).
The SBPH400 also has a number of pins which are intended for use during production test
only, and are held to ground or VDD as appropriate in normal operation.
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