Pin Descriptions
Pin Names
HD
DIR
A1–A8
B1–B8
A9–A13
Y9–Y13
A14–A17
C14–C17
PLHIN
PLH
HLHIN
HLH
Description
HIGH Drive Enable Input (Active HIGH)
Direction Control Input
Inputs or Outputs
Inputs or Outputs
Inputs
Outputs
Outputs
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
Host Logic HIGH Input
Host Logic HIGH Output
Logic Diagram
Truth Table
Inputs
DIR
HD
Outputs
L
L B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
L
H B1–B 8 Data to A1–A8, and
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
H
L A1–A8 Data to B1–B8 (Note 2)
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
H
H A1–A8 Data to B1–B8
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
Note 1: Y9–Y13 Open Drain Outputs
Note 2: B1–B8 Open Drain Outputs
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