HFA3783 Просмотр технического описания (PDF) - Intersil

Номер в каталоге

Компоненты Описание

Список матч

HFA3783

I/Q Modulator/Demodulator and Synthesizer

Intersil 

HFA3783

DC Offset Calibration Counter

BIT

DESCRIPTION

C(0-6)

Least Significant bit C(0) to Most significant bit C(6) of the offset calibration counter/divider. The calibration clock frequency and

calibration time is defined by the Reference signal frequency divided down by this counter as follows:

CAL TIME = 22 ∗ R-----E----F--2--I-N--∗----(--CM-----H-----z---)

C(11)

Set output bias level for AC coupling applications and TX/RX switching improvement in performance.

CLK WIDTH

HIGH

CLK/LE

SET UP

CLK

DATA

LE

MSB

BIT 20

CLK WIDTH

LOW

BIT 2

LSB

BIT 1

DAT/CLK

SET UP

DAT/CLK

HOLD

FIGURE 1. PLL SYNTHESIZER SERIAL INTERFACE TIMING DIAGRAM

LE

P. WIDTH

12

Share Link: