LP62E16128A-T(2003) Просмотр технического описания (PDF) - AMIC Technology

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LP62E16128A-T
(Rev.:2003)

128K X 16 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise And Fall Time

Input and Output Timing Reference Levels

Output Load

LP62E16128A-T Series

0.2V to VCC - 0.2V

5 ns

0.9V

See Figures 1 and 2

TTL

TTL

CL

30pF

CL

5pF

* Including scope and jig.

* Including scope and jig.

Figure 1. Output Load

Data Retention Characteristics (TA = -25°C to 85°C)

Symbol

Parameter

VDR

VCC for Data Retention

Figure 2. Output Load for tCLZ, tOLZ,

tCHZ, tOHZ, tWHZ, and tOW

Min.

1.2

Max. Unit

Conditions

2.2

V CE ≥ VCC - 0.2V

ICCDR

Data Retention Current

VCC = 1.2V,

-

3*

µA CE ≥ VCC - 0.2V

VIN ≥ 0V

tCDR

Chip Disable to Data Retention Time

0

-

tR

Operation Recovery Time

tRC

-

tVR

VCC Rising Time from Data Retention

Voltage to Operating Voltage

5

-

* LP62E16128A-70LLT

ICCDR: max. 1µA at TA = 0°C to + 40°C

ns

ns See Retention Waveform

ms

(December, 2003, Version 1.3)

12

AMIC Technology, Corp.

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