EL4584C Просмотр технического описания (PDF) - Elantec -> Intersil

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EL4584C

Horizontal Genlock, 4 FSC

Elantec -> Intersil 

EL4584C

Horizontal Genlock 4 FSC

Timing Diagrams

PLL Locked Condition (Phase Error e 0)

Falling edge of H-sync a 110 ns locks to rising edge of Ext Div signal

Out of Lock Condition

4584 – 2

iE

e

Ti

TH

c

360

TH e H-sync period

Ti e phase error period

Test Circuit 1

4584 – 3

4584 – 5

4

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