MX7672(2012) Просмотр технического описания (PDF) - Maxim Integrated

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MX7672
(Rev.:2012)

High-Speed 12-Bit ADC With External Reference Input Part

Maxim Integrated 

MX7672

High-Speed 12-Bit ADC With External

Reference Input Part

Timing Characteristics

(VDD = +5V, VSS = -12V, 100% production tested, unless otherwise noted.) (Note 3, Figures 7, 9, 10)

PARAMETER

SYMBOL CONDITIONS

CS to RD Setup Time

(Note 2)

RD to BUSY Delay

Data-Access Time (Note 4)

RD Pulse Width (Note 2)

CS to RD Hold Time

(Note 2)

Data-Setup Time After

BUSY (Note 4)

Bus-Relinquish Time

(Note 5)

Delay Between Read

Operations

CLKIN to BUSY Delay

(Note 2)

RD to CLKIN Setup/Hold

Time (Notes 2, 6)

t1

t2 CL = 50pF

t3 CL = 100pF

t4

t5

t6 CL = 100pF

t7

t8

t9

t10

TA = +25°C

ALL GRADES

MIN TYP MAX

0

70 190

50 125

t3

0

40 70

30 75

200

120

25

100

TA = TMIN to TMAX

MX7672K/L/B/C

MIN TYP MAX

0

230

150

t3

0

90

85

200

150

25

100

TA = TMIN to TMAX

MX7672T/U

MIN TYP MAX

UNITS

0

ns

270 ns

170 ns

t3

ns

0

ns

100 ns

90

ns

200

ns

180 ns

25

100 ns

Note 1: VDD = +5V, VSS = -12V, 1 LSB = FS/4096. Performance over power-supply tolerance is guaranteed by power-supply rejec-

tion test.

Note 2: Guaranteed by design.

Note 3: All inputs are 0 to +5V swing with tr = tf = 5ns (10% to 90% of +5V) and timed from a voltage level of +1.6V.

Note 4: t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross +0.8V or

+2.4V.

Note 5: t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuit of Figure 2.

Note 6: For predictable conversion times, RD to CLKIN falling edge must be outside this window. If t10 < 25ns, conversion will skip

first falling CLKIN edge and start on second falling CLKIN edge. If t10 > 100ns, conversion will start on first falling CLKIN

edge.

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