CDP1853/3 Просмотр технического описания (PDF) - Intersil
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CDP1853/3 Datasheet PDF : 7 Pages
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CDP1853/3, CDP1853C/3
CDP1800 SERIES
N0 N1 N2 TPA TPB MRD BUS
TPA
CDP1853
DECODED 1
“61” INSTRUCTION
DATA BUS
CL CS1
CS2 CDP1852
NO, N1, N2
CLOCK A
CLOCK B
CE
CDP1853
“62 - 6F”
INST.
I/O
7 INPUT,
6 OUTPUT
PORTS
NO, N1, N2
SECTIONS 3 - 7
CLOCK A
CLOCK B
CE
CDP1853
“62 - 6F”
INST.
I/O
7 INPUT,
6 OUTPUT
PORTS
NO, N1, N2
CLOCK A
CLOCK B
CE
CDP1853
“62 - 6F”
INST.
I/O
7 INPUT,
6 OUTPUT
PORTS
NOTE:
1. System shown will select up to 56 input and 48 output ports. With additional decoding, the total number of input and output ports can be
further expanded.
FIGURE 6. TWO LEVEL I/O USING CDP1853 AND CDP1852
Bias/Static Burn-In Circuit
VDD
VSS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
NOTE:
1. All resistors are 47kΩ ±20%.
VDD
TYPE
CDP1853C
VSS
VDD
VDD
7V
TEMPERATURE TIME
+125oC
160 Hrs.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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