EP7211-CV-A Просмотр технического описания (PDF) - Cirrus Logic

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EP7211-CV-A

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Cirrus Logic 

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Function

Signal

Name

Signal

Description

PE[0]/

BOOTSEL0

PE[1]/

BOOTSEL1

PE[2]/

CLKSEL

PWM

Drives

Boundary

Scan

Test

DRIVE[0–1]

FB[0–1]

TDI

TDO

TMS

TCLK

TNRST

NTEST[0–1]

Oscillators

MOSCIN

MOSCOUT

RTCIN

RTCOUT

I/O

Port E I/O (3 bits only). Can be used as general purpose I/O during normal

operation.

I/O

During power-on reset, PE[0] and PE[1] are inputs and are latched by the ris-

ing edge of NPOR to select the memory width that the

EP7211 will use to read from the boot code storage device (e.g., external 8-bit-

wide Flash bank).

I/O

During power-on reset, PE[2] is latched by the rising edge of NPOR to select

the clock mode of operation (i.e., either the PLL or external

13 MHz clock mode).

I/O

PWM drive outputs. These pins are inputs on power up to determine what

polarity the output of the PWM should be when active. Otherwise, these pins

are always an output.

I

PWM feedback inputs

I

JTAG data in

O

JTAG data out

I

JTAG mode select

I

JTAG clock

I

JTAG async reset

I

Test mode select inputs. These pins are used in conjunction with the power-on

latched state of NURESET.

I

Main 3.6864 MHz oscillator for 18.432MHz–73.728 MHz PLL

O

I

Realtime clock 32.768 kHz oscillator

O

NOTE:

.

See table below for pin assignment and direction following pin multiplexing.

Table 2-1. SSI/Codec/MCP Pin Multiplexing

SSI2

SSICCLK

SSITXFR

SSITXDA

SSIRXDA

SSIRXFR

Codec

PCMCLK

PCMSYNC

PCMOUT

PCMIN

p/u*

MCP

SIBCLK

SIBSYNC

SIBDOUT

SIBDIN

p/u*

Direction

I/O

I/O

Output

Input

I/O

Strength

1

1

1

1

* p/u = use an ~10 k pull-up

18

Pin Information

DS352PP3

JUL 2001

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