CS89712-CB Просмотр технического описания (PDF) - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

2.8.1 Interrupt Latencies

2.8.1.1 Operating State

The ARM720T core checks for a low level on its

FIQ and IRQ inputs at each instruction boundary.

The interrupt latency is therefore directly related to

the amount of time it takes to complete execution

of the current instruction when the interrupt condi-

tion is detected. First, there is a one to two clock cy-

cle synchronization penalty. For the case where the

CS89712 is operating with a 16-bit external mem-

ory system, and the program stored in one wait

state FLASH memory, the worst-case interrupt la-

tency is 251 clock cycles. This includes a delay for

cache line fills for instruction prefetches, and a data

abort occurring at the end of the LDM instruction,

and the LDM being non-quad word aligned. In ad-

dition, the worst-case interrupt latency assumes

that LCD DMA cycles to support a panel size of

320 x 240 at 4 bits-per-pixel, 60 Hz refresh rate, is

in progress. This would give a worst-case interrupt

latency of about 3.4 µs for 74 MHz operation. For

operation at different frequencies and/or with

32 bit wide external memory, the latency will

change accordingly.

For the nMEDCHG signal, this figure is substan-

tially increased by the maximum time required to

pass through the deglitcher, approximately 125 µs

(2 cycles of the 16.384 kHz clock derived from the

RTC oscillator). This results in an absolute worst-

case latency of approximately 128 µs. Refer to

Table 10 for a summary.

All the serial data transfer peripherals included in

the CS89712 (except for the master-only SSI1)

have local buffering to ensure a reasonable inter-

rupt latency response requirement for the OS of <

1 ms. This assumes that the design data rates do not

exceed the data rates described in this specification.

If the OS cannot meet this requirement, there will

be a risk of data over/underflow occurring.

2.8.1.2 Idle State

When leaving the Idle State as a result of an inter-

rupt, the CPU clock is restarted after approximately

two clock cycles. However, there is still potentially

up to a 251 clock latency as described in the first

section above, unless the code is written to include

at least two single cycle instructions immediately

after the write to the IDLE register (in which case

the latency drops to a few microseconds). This is

important, as the Idle State can only be left because

of a pending interrupt, which has to be synchro-

nized by the processor before it can be serviced.

2.8.1.3 Standby State

In the Standby State, the latency will depend on

whether the system clock is shut down and if the

FASTWAKE bit in the SYSCON3 register is set. If

the system is configured to run from the internal

PLL clock, then the PLL will always be shut down

when in the Standby State. In this case, if the

FASTWAKE bit is cleared, then there will be a la-

tency of between 0.125 sec to 0.25 sec. If the

FASTWAKE bit is set, then there will be a latency

of between 250 µsec to 500 µsec.

Whenever the CS89712 is in the Standby State, the

external address and data buses are driven low. The

RUN signal is used internally to force these buses

to be driven low. This prevents de-powered periph-

erals from draining current. Also, the internal pe-

ripheral’s signals are set to their Reset State.

2.8.1.4 Snooze State

In Snooze State, the latency will be reduced to the

same as for the Idle State described above. This is

true at any frequency because the PLL or external

clock source is not stopped. All clocks except the

minimum required for LCD refresh from the inter-

nal SRAM are disabled to save further power.

To drastically reduce the potential worst case laten-

cy when leaving Snooze State to a few microsec-

onds, ensure that the code contains two single cycle

20

DS502PP2

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