EP7312-EB-90 Просмотр технического описания (PDF) - Cirrus Logic
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EP7312-EB-90
Cirrus Logic
EP7312-EB-90 Datasheet PDF : 64 Pages
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EP7312
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter
SDCLK rising edge to SDCS assert delay time
SDCLK rising edge to SDCS deassert delay time
SDCLK rising edge to SDRAS assert delay time
SDCLK rising edge to SDRAS deassert delay time
SDCLK rising edge to SDRAS invalid delay time
SDCLK rising edge to SDCAS assert delay time
SDCLK rising edge to SDCAS deassert delay time
SDCLK rising edge to ADDR transition time
SDCLK rising edge to ADDR invalid delay time
SDCLK rising edge to SDMWE assert delay time
SDCLK rising edge to SDMWE deassert delay time
DATA transition to SDCLK rising edge time
SDCLK rising edge to DATA transition hold time
SDCLK rising edge to DATA transition delay time
Symbol
tCSa
tCSd
tRAa
tRAd
tRAnv
tCAa
tCAd
tADv
tADx
tMWa
tMWd
tDAs
tDAh
tDAd
Min
0
−3
1
−3
2
−2
−5
−3
−2
−2
−4
-
-
0
Typ
2
2
3
1
4
2
0
1
2
1
0
-
-
-
Max
4
10
7
10
7
5
3
5
5
5
4
2
1
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
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