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PCK2057DGG

70 – 190 MHz I2C differential 1:10 clock driver

NXP Semiconductors. 

Philips Semiconductors

70 – 190 MHz I2C differential 1:10 clock driver

Product data

PCK2057

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions.

SYMBOL

PARAMETER

VIK

Input voltage

All inputs

VOH

HIGH-level output voltage

VOL

VOX

II

IOZ

IDDPD

IDD

AIDD

IDDI2C

LOW-level output voltage

SDA

Output differential cross voltage

Input current

CLK, FBIN

High impedance state output current

Power-down current on VDDQ + AVDD

Power-down current on VDDI2C

Dynamic current on VDDQ

Supply current on AVDD

Supply current on VDDI2C

CI

Input capacitance

NOTES:

1. All typical values are at respective nominal VDDQ.

TEST CONDITIONS

VDDQ = 2.3 V; II = –18 mA

VDDQ = min to max; IOH = –1 mA

VDDQ = 2.3 V; IOH = –12 mA

VDDQ = min to max; IOL = 1 mA

VDDQ = 2.3 V; IOL = 12 mA

VDDI2C = 3.0 V; IOL = 3 mA

VDDQ = 2.7 V; VI = 0 V to 2.7 V

VDDQ = 2.7 V; VO = VDDQ or GND

CLK at 0 MHz; Σ of IDD and AIDD

CLK at 0 MHz; VDDQ = 3.6 V

fO = 100 MHz

fO = 100 MHz

VDDI2C = 3.6 V;

SCL and SDA = 3.6V

VDDQ = 2.5 V; VI = VDDQ or GND

MIN

—

VDDQ – 0.1

1.7

—

—

—

VDDQ/2 – 0.2

—

—

—

—

—

—

—

2

LIMITS

TYP1

—

—

—

—

—

—

VDDQ/2

—

—

150

3

205

4

1

2.8

MAX

–1.2

—

—

0.1

0.6

0.4

VDDQ/2 + 0.2

±10

±10

250

20

230

6

UNIT

V

V

V

V

V

V

V

µA

µA

µA

µA

mA

mA

2

mA

3

pF

TIMING REQUIREMENTS

Over recommended ranges of supply voltage and operating free-air temperature.

SYMBOL

PARAMETER

LIMITS

MIN

MAX

UNIT

fCLK

Clock frequency

70

190

MHz

Input clock duty cycle

40

60

%

Stabilization time 1

—

100

µs

NOTE:

1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,

a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation

delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input

modulation under SSC application.

TIMING REQUIREMENTS FOR THE I2C INTERFACE

Over recommended ranges of operating free-air temperature and VDDI2C from 3.3 V to 3.6 V..

SYMBOL

PARAMETER

fSCL

tBUF

tSU;STA

tHD;STA

tLOW

tHIGH

tr

tf

tSU;DAT

tHD;DAT

tSU;STO

SCL clock frequency

Bus free time between a STOP and START condition

Set-up time for a repeated START condition

Hold time (repeated) START condition. After this period, the first clock is generated.

LOW period of the SCL clock

HIGH period of the SCL clock

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

DATA set-up time

DATA hold time

Set-up time for STOP condition

STANDARD-MODE I2C-BUS

MIN

MAX

—

100

4.7

—

4.7

—

4.0

—

4.7

—

4.0

—

—

1000

—

300

250

—

0

—

4

—

UNIT

kHz

µs

µs

µs

µs

µs

ns

ns

ns

ns

µs

2001 Jun 12

7

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