V61C518256-10N Просмотр технического описания (PDF) - Mosel Vitelic, Corp
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V61C518256-10N Datasheet PDF : 12 Pages
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MOSEL VITELIC
Pin Descriptions
A0–A14 Address Inputs
These 15 address inputs select one of the 32,768 x
8 bit segments in the RAM.
CE
Chip Enable Inputs
CE is an active LOW input. Chip Enable must be
LOW when reading from or writing to the device.
When HIGH, the device is in standby mode with I/O
pins in the high impedance state.
OE
Output Enable Input
The Output Enable input is active LOW. When OE
is LOW with CE LOW and WE HIGH, data of the
selected memory location will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.
V61C518256
WE
Write Enable Input
An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be
written into the selected memory location.
I/O0–I/O7 Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
VCC
GND
Power Supply
Ground
Pin Configurations (Top View)
28-Pin SOJ
A14
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
I/O0
11
I/O1
12
I/O2
13
GND 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
518256-01
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
28-Pin TSOP (Standard)
22
21
A10
23
20
CE
24
19
I/O7
25
18
I/O6
26
17
I/O5
27
16
I/O4
28
15
I/O3
1
14
GND
2
13
I/O2
3
12
I/O1
4
11
I/O0
5
10
A0
6
9
A1
7
8
A2
518256-03
V61C518256 Rev. 0.3 July 1998
2
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