MCM69F536C Просмотр технического описания (PDF) - Motorola => Freescale
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MCM69F536C Datasheet PDF : 12 Pages
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APPLICATION INFORMATION
The MCM69F536C BurstRAM is a high speed synchro-
nous SRAM that is intended for use primarily in secondary or
level two (L2) cache memory applications. L2 caches are
found in a variety of classes of computers — from the desk-
top personal computer to the high–end servers and trans-
action processing machines. For simplicity, the majority of L2
caches today are direct mapped and are single bank imple-
mentations. These caches tend to be designed for bus
speeds in the range of 33 to 66 MHz. At these bus rates,
flow–through (non–pipelined) BurstRAMs can be used since
their access times meet the speed requirements for a mini-
mum–latency, zero–wait state L2 cache interface. Latency is
a measure (time) of “dead” time the memory system exhibits
as a result of a memory request.
For those applications that demand bus operation at great-
er than 66 MHz or multi–bank L2 caches at 66 MHz, the pipe-
lined (register/register) version of the 32K x 36 BurstRAM
(MCM69P536) allows the designer to maintain zero–wait
state operation. Multiple banks of BurstRAMs create addi-
tional bus loading and can cause the system to otherwise
miss its timing requirements. The access time (clock–to–
valid–data) of a pipelined BurstRAM is inherently faster than
a non–pipelined device by a few nanoseconds. This does not
come without cost. The cost is latency — “dead” time.
For L2 cache designs that must minimize both latency and
wait states, flow–through BurstRAMs are the best choice in
achieving the highest performance in L2 cache design.
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for 68K–,
PowerPC–, 486–, i960–, and Pentium–based systems,
these SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous inter-
face can make use of the MCM69F536C. The burst counter
feature of the BurstRAM can be disabled, and the SRAM can
be configured to act upon a continuous stream of addresses.
See Figure 2.
CONTROL PIN TIE VALUES EXAMPLE (H ≥ VIH, L ≤ VIL)
Non–Burst ADSP ADSC ADV SE1 SE2 LBO
Sync Non–Burst, H
Flow–Through
SRAM
L
H
L
H
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
K
ADDR
A
B
C
D
SE3
W
E
F
G
H
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 2. Example Configuration as Non–Burst Synchronous SRAM
MCM69F536C
10
MOTOROLA FAST SRAM
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