V436632Z24VBTG-10PC Просмотр технического описания (PDF) - Mosel Vitelic, Corp
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V436632Z24VBTG-10PC
Mosel Vitelic, Corp
V436632Z24VBTG-10PC Datasheet PDF : 12 Pages
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MOSEL VITELIC
SPD-Table
Byte
Number
28
29
30
31
32
33
34
35
62-61
62
63
64
65-71
72
73-90
91-92
93
94
95-98
99-125
126
127
128+
Function Described
SPD Entry Value
Minimum Row Active to Row Active Delay
tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (Per Bank)
14 ns/15 ns/16 ns
15 ns/20 ns
42 ns/45 ns
256 Mbyte
SDRAM Input Setup Time
1.5 ns/2.0 ns
SDRAM Input Hold Time
0.8 ns/1.0 ns
SDRAM Data Input Setup Time
1.5 ns/2.0 ns
SDRAM Data Input Hold Time
0.8 ns/1.0 ns
Superset Information (May be used in Fu-
ture)
SPD Revision
Revision 2/1.2
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Mosel Vitelic
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
1 = US, 2 = Taiwan
Module Part Number (ASCII)
V436632Z24V
PCB Identification Code
Current PCB Revision
Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
Assembly Manufacturing Date (Week) Binary Coded week (BCD)
Assembly Serial Number
byte 95 = LSB, byte 98 =
MSB
Reserved
Intel Specification for Frequency
Reserved
Unused Storage Location
-75PC
0E
0F
2A
40
15
08
15
08
00
02
FD
40
00
00
64
00
00
V436632Z24V
Hex Value
-75
0F
-10PC
10
14
14
2D
2D
40
40
15
20
08
10
15
20
08
10
00
00
02
12
42
B0
40
40
00
00
00
00
64
64
00
00
00
00
V436632Z24V Rev. 1.1 February 2002
5
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