HIP4080A/81AEVALZ Просмотр технического описания (PDF) - Intersil

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HIP4080A/81AEVALZ

HIP4080A, 80V High Frequency H-Bridge Driver

Intersil 

Application Note 9404

Since the internal charge pump offsets any possible diode

leakage and upper drive circuit bias currents, these sources

of discharge current for the bootstrap capacitor will be

ignored. The bootstrap capacitance required for the example

above can be calculated as shown in Equation 4, using

Equation 2.

CBS

=

-1---8---n---C------+-----1----2---.--5---n----C---

12.0 - 11.0

(EQ. 4)

Therefore a bootstrap capacitance of 0.033µF will result in

less than a 1.0V droop in the voltage across the bootstrap

capacitor during the turn-on period of either of the upper

MOSFETs. If typical values of gate charge and bootstrap

diode recovered charge are used rather than the maximum

value, the voltage droop on the bootstrap supply will be only

about 0.5V

Power Dissipation and Thermal Design

One way to model the power dissipated in the HIP4080A is

by lumping the losses into static losses and dynamic

(switching) losses. The static losses are due to bias current

losses for the upper and lower sections of the IC and include

the sum of the ICC and IDD currents when the IC is not

switching. The quiescent current is approximately 9mA.

Therefore with a 12V bias supply, the static power

dissipation in the IC is slightly over 100mW.

The dynamic losses associated with switching the power

MOSFETs are much more significant and can be divided into

the following categories:

• Low Voltage Gate Drive (charge transfer)

• High Voltage Level-shifter (V-I) Losses

• High Voltage Level-shifter (charge transfer)

In practice, the high voltage level-shifter and charge transfer

losses are small compared to the gate drive charge transfer

losses.

The more significant low voltage gate drive charge transfer

losses are caused by the movement of charge in and out of

the equivalent gate-source capacitor of each of the 4

MOSFETs comprising the H-bridge. The loss is a function of

PWM (switching) frequency, the applied bias voltage, the

equivalent gate-source capacitance and a minute amount of

CMOS gate charge internal to the HIP4080A. The low

voltage charge transfer losses are given by Equation 5.

PSWLO = fPWM × (QG + QIC) × VBIAS

(EQ. 5)

The high voltage level-shifter power dissipation is much

more difficult to evaluate, although the equation which

defines it is simple as shown in Equation 6. The difficulty

arises from the fact that the level-shift current pulses, ION

and IOFF, are not perfectly in phase with the voltage at the

upper MOSFET source terminals, VSHIFT due to propagation

delays within the IC. These time-dependent source voltages

(or “phase” voltages) are further dependent on the gate

capacitance of the driven MOSFETs and the type of load

(resistive, capacitive or inductive) which determines how

rapidly the MOSFETs turn on. For example, the level-shifter

ION and IOFF pulses may come and go and be latched by the

upper logic circuits before the phase voltage even moves. As

a result, little level-shift power dissipation may result from the

iON pulse, whereas the IOFF pulse may have a significant

power dissipation associated with it, since the phase voltage

generally remains high throughout the duration of the iOFF

pulse.

∫ PSHIFT

=

--I-

T

T

O

(IO

N

(

t

)

+

IOF

F(

t)

)

×

VS

HIFT

(

t

)

×

dt

(EQ. 6)

Lastly, there is power dissipated within the IC due to charge

transfer in and out of the capacitance between the upper

driver circuits and VSS. Since it is a charge transfer

phenomena, it closely resembles the form of Equation 5,

except that the capacitance is much smaller than the

equivalent gate-source capacitances associated with power

MOSFETs. On the other hand, the voltages associated with

the level-shifting function are much higher than the voltage

changes experienced at the gate of the MOSFETs. The

relationship is shown in Equation 7.

PTUB = CTUB × VS2 HIFT × fPWM

(EQ. 7)

The power associated with each of the two high voltage tubs

in the HIP4080A derived from Equation7 is quite small, due

to the extremely small capacitance associated with these

tubs. A “tub” is the isolation area which surrounds and

isolates the high side circuits from the ground referenced

circuits of the IC. The important point for users is that the

power dissipated is linearly related to switching frequency

and the square of the applied bus voltage.

The tub capacitance in Equation 7 varies with applied

voltage, VSHIFT, making its solution difficult, and the phase

shift of the ION and IOFF pulses with respect to the phase

voltage, VSHIFT, in Equation 6 are difficult to measure. Even

the QIC in Equation 5 is not easy to measure. Hence the use

of Equation 5 through Equation 7 to calculate total power

dissipation is at best difficult. The equations do, however,

allow users to understand the significance that MOSFET

choice, switching frequency and bus voltage play in

determining power dissipation. This knowledge can lead to

corrective action when power dissipation becomes

excessive.

Fortunately, there is an easy method which can be used to

measure the components of power dissipation rather than

calculating them, except for the tiny “tub capacitance”

component.

8

AN9404.3

December 11, 2007

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