V54C316162VC-6 Просмотр технического описания (PDF) - Mosel Vitelic, Corp

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V54C316162VC-6

200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

V54C316162VC

5. Burst Write Operation

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND NOP

WRITE A

NOP

NOP

NOP

NOP

NOP

NOP

NOP

I/O’s

DIN A0

DIN A1

DIN A2

DIN A3

don’t care

The first data element and the Write

are registered on the same clock edge.

5.1 Write to Precharge

Extra data is ignored after

termination of a Burst.

T0

T1

T2

T3

T4

T5

CLK

COMMAND NOP

I/O’S

WRITE

NOP

NOP

NOP

NOP

tRDL

DIN A0

DIN A1

DIN A2

DIN A3

T6

PRE

T7

T8

NOP

NOP

6.1 Write Interrupted by a Write

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND NOP

I/O’s

WRITE A WRITE B

tCDL

DIN A0

DIN B0

NOP

DIN B1

NOP

DIN B2

NOP

DIN B3

NOP

NOP

NOP

V54C316162VC Rev. 1.4 December 2001

17

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