PDM41256LA8T Просмотр технического описания (PDF) - Unspecified
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PDM41256LA8T Datasheet PDF : 8 Pages
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PDM41256
Read Cycle No. 1(1)
Read Cycle No. 2(2)
AC Electrical Characteristics
Description
--7(6)
--8(6)
-10(6)
-12
-15
READ Cycle
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
READ cycle time
tRC
7
8
10
12
15
ns
Address access time
tAA
7
8
10
12
15 ns
Chip enable access time
tACE
7
8
10
12
15 ns
Output hold from address change
Chip enable to output in low Z(3, 4, 5)
Chip disable to output in high Z(3, 4, 5)
Chip enable to power up time(4)
Chip disable to power down time(4)
tOH
3
tLZCE 5
tHZCE
tPU
0
tPD
3
3
3
3
ns
5
5
5
5
ns
5
6
6
6
6 ns
0
0
0
0
ns
7
8
10
12
15 ns
Output enable access time
tAOE
5
5
5
6
8 ns
Output enable to output in low Z(4, 5)
tLZOE 0
0
0
0
0
ns
Output disable to output in high Z(4, 5)
tHZOE
5
6
6
6
6 ns
SHADED AREA = PRELIMINARY DATA.
Notes referenced are after Data Retention Table.
1
2
3
4
5
6
7
8
9
10
11
12
Rev. 2.0 - 7/17/96
3-37
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