MSU2032C25P Просмотр технического описания (PDF) - Mosel Vitelic, Corp

Номер в каталоге

Компоненты Описание

Список матч

MSU2032C25P

8 - bit single chip microcontroller

Mosel Vitelic, Corp 

MOSEL VITELIC

MSU2052/U2032

Power Down Mode

It saves the RAM content, stops the clock generator

and disables every other blocks' function until the

coming hardware reset. To save even more power

consumption, user's software program can invoke this

mode. The SFRs and the on-chip data RAM retain

their values during this mode, but the porcessor stops

executing instructions. In Power-Down mode (PD=1)

the oscillator is frozen.

-An instruction that sets flag (PCON.1) causes that to

be the last instruction executed before going into the

Power Down Mode.

-In the Power Down Mode, the on-chip oscillator is

stopped.

With the clock frozen, all functions are stopped, but

the on-chip RAM and Special Function Registers are

held.

-Reset redefines all the SFRs, but does not change the

on-chip RAM.

-There are two ways to terminate the Power Down

Mode.

1) By hardware reset

All SFR and PC value will be cleared to reset value.

2) One of CLK, DATA, PORT 2.0-2.7 transition to low

(falling edge trigger)

After the program wakes up, the PC value will be

0023h (if enable IE register) and execute interrupt

service routine and then returns to PC+1 address after

the program wakes up.

-Care must be taken, however, to ensure that VCC is

not reduced before the Power Down Mode is invoked,

and that VCC is restored to its normal operating level

before the Power Down Mode is terminated.

-The hardware reset must be held active long enough

to allow the oscillator to restart and stabilize.

General of above

User should fix the attention on using wake up from

port 2:

-The user should write the power down or idle mode

flag value to one RAM address before write PCON to

distinguish waking up from power down mode or idle

mode.

-After idle mode or power down mode wakes up, the

interrupt service routine will be executed first and then

executes PC+1 address if the IE register is enabled

before entering power down mode or idle mode. The

interrupt service routine will not be executed but CPU

executes PC+1 address program if disable IE register.

-After wake up power down or idle mode the IDF flag

will be set by hardware. The IDF flag be cleared at

the ISR execution time. If IE register is disable, the

IDF flag will not be cleared when power down or idle

mode wakes up.

Mode

Idle

Idle

Power Down

Power Down

The state of pins during Idle and Power-Down Mode

Program

memory

Internal

External

Internal

External

ALE

1

1

0

0

#PSEN

1

1

0

0

Port 0

Data

Float

Data

Float

Port 1 Port 2

Data

Data

Data

Data

Data

Address

Data

Data

Port 3

Data

Data

Data

Data

Absolute Maximal Rating

Symbol

Vdd - Vss

Name

DC supply Voltage

Rating

Unit

-0.5 ~ +5.0

V

-0.5 ~ +7.0

V

VIN

Input voltage

Vss-0.3 ~ Vdd+0.3 V

VOUT

output voltage

Vss ~ Vdd

T (Operating) Operating Temperature

0 ~ +70

°C

T (Storage) Storage Temperature

-55 ~ +125

°C

Remark

U20x1L

U20x1S,U20x1C

* Note:

Operation beyond Absolute Maximal Rating

can adversely affect device reliability.

Rev. 1.0 February 1998

6

Share Link: