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CS5126 Просмотр технического описания (PDF) - Cherry semiconductor

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CS5126 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Electrical Characteristics: -40°C TJ 125°C, -40°C TA 105°C, 7.60V VCC 20V, UVLO = 3.0V, ISENSE = 0V,
CV(CC) = 0.33µF, CGATE = 1nF (ESR = 10), CSS = 470pF CV(FB) = 100pF, unless otherwise stated.
PARAMETER
s VCC Clamp and BIAS Pin
VCC Clamp Voltage
BIAS Minimum Voltage
BIAS Clamp
TEST CONDITIONS
MIN
TYP
MAX
CS5124 Only. Connect an NFET as follows: BIAS = G, VCC = S, VIN = D.
36V VIN 60V, 220nF
CSS 500nF, R = 500k
7.275
7.9
8.625
Measure Voltage on BIAS with:
1.6
2.8
4
10V VCC 20V and 50µA IBIAS 1mA
With BIAS pin sinking 1mA
12
15
20
UNIT
V
V
V
s 200kHz Oscillator
Operating Frequency
Max Duty Cycle Clamp
Slope Compensation
(Normal operation)
Slope Compensation
(Synchronized operation)
SYNC Input Threshold Voltage
SYNC Input Impedance
CS5126 Only
(Note 1)
Measured with SYNC = 1V &10V
175
200
78
82.5
12
18
7
12
1
2
50
120
225
kHz
85
%
23 mV/µs
16 mV/µs
3
V
230
k
s 400kHz Oscillator
Operating Frequency
Max Duty Cycle Clamp
Slope Compensation
CS5124 Only
360
400
440
kHz
80.0
82.5
85.0
%
15
21
26 mV/µs
s Soft Start
Soft Start Charge Current
Soft Start Discharge Current
VSS Voltage when VFB
Begins to Rise
VFB = 300mV
Peak Soft Start Charge Voltage
Valley Soft Start Discharge Voltage
7
10
13
µA
0.5
10.0
mA
1.40
1.62
1.80
V
4.7
4.9
V
200
275
400
mV
s Current Sense
CS5124 Only
First Current Sense Threshold At max duty cycle.
Second Current Sense Threshold
ISENSE to GATE Prop. Delay
0 to 700mV pulse into ISENSE
(after blanking time)
Leading Edge Blanking Time
Internal Offset
0 to 400mV pulse into ISENSE
(Note 1)
170
195
215
mV
250
275
315
mV
60
90
130
ns
90
130
180
ns
60
mV
s Current Sense
First Current Sense Threshold
Second Current Sense
Threshold
ISENSE to GATE Prop. Delay
Leading Edge Blanking Time
Internal Offset
CS5126 Only
At max duty cycle
0 to 800mV pulse into ISENSE
(after blanking time)
0 to 550mV pulse into ISENSE
(Note 1)
300
335
485
525
60
90
110
175
125
360
mV
575
mV
130
ns
210
ns
mV
3

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