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IDT7210L55G

16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR

Integrated Device Technology 

IDT7210L

16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

11

NC X15 RND ACC CLKY TC PREL CLKP P33

10 X13 X14 TSL SUB CLKX VCC TSX TSM P34 P32 NC

09 X11 X12

P30 P31

08

X9 X10

P28 P29

07 X7 X8

P26 P27

06 X5 X6

G68-2

P24 P25

05 X3 X4

P22 P23

04

X1 X2

P20 P21

03

Y0,

P0 X0

P18 P19

02

NC

Y1,

P1

Y3,

P3

Y5,

P5

Y7,

P7

Y8,

P8

Y10, Y12, Y14,

P10 P12 P14

P16

P17

01

Y2, Y4, Y6, GND Y9, Y11, Y13, Y15, NC

P2 P4 P6

P9 P11 P13 P15

Pin 1

Designator A

B

C

D

E

F

G

H

J

K

L

PGA

2577 drw 05

TOP VIEW

PIN DESCRIPTIONS

Pin Name

I/O

Description

X0 - 15

I Data Inputs

Y0 - 15/ P0 - 15

P16 - 31

I/O Multiplexed I/O port. Y0 - 15 are data inputs and can be used to preload LSP register on PREL = 1. P0 - 15

are LSP register outputs - enabled by TSL.

I/O MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1.

P32 - 34

CLKX

I/O XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when

PREL = 1.

I Input data X0 - 15 loaded in X input register on CLKX rising edge.

CLKY

I Input data Y0 - 15 loaded in Y input register on CLKY rising edge.

CLKP

I Output data loaded into output register on rising edge of CLKP.

TSX

I TSX = 0 enables XTP outputs, TSX = 1 tristates P32 - 34 lines.

TSM

I TSM = 0 enables MSP outputs, TSM = 1 tristates P16 - 31 lines.

TSL

I TSL = 0 enables LSP outputs, TSL = 1 tristates P0 - 15 lines.

PREL

I When PREL= 1 data is input on P0 - 15 lines. When PREL = 0, inputs on these lines are ignored.

ACC

SUB

TC

RND

I This input is loaded into the control register on the rising edge of (CLKX + CLKY).

When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a

subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a

simple multipler with no accumulation

I This input is loaded into the control register on the rising edge of (CLKX + CLKY).

This input is active only when ACC = 1. When SUB = 1 the contents of the output register are subtracted

from the result and stored back in the output register. When SUB = 0 the contents of the output register

are added to the result and stored back in the output register

I This input is loaded into the control register on the rising edge of (CLKX + CLKY).

When TC = 1, the X and Y input are assumed to be in two's complement form. When TC = 0, X and Y

inputs are assumed to be in unsigned magnitude form

I This input is loaded into the control register on the rising edge of (CLKX + CLKY).

RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and

XTP data

2577 tbl 01

11.2

3

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