ML4900CT Просмотр технического описания (PDF) - Micro Linear Corporation
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ML4900CT Datasheet PDF : 8 Pages
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5VIN
12VIN
OUTEN
UP#
VID0
VID1
VID2
VID3
D1
BAW56
PWRGD
C8
220nF
16V
ML4900
C11
C10
22µF
220nF
25V
16V
C13
1µF
ML4900
16V
1 D0
PROTECT 16
2 D1
3 D2
VDD 15
N DRV H 14
4 D3
5 SHDN
N DRV L 13
PWR GND 12
6 PWR GOOD
COMP 11
7 VREF
8 GND
ISENSE 10
VFB 9
R3
330kΩ
C9
33pF
R4
1kΩ
R5
100kΩ
C12
220nF
16V
Q1
Q2
R1
5mΩ
1W
3X C1 C2 C3
1800µF
10V
L2
1.4µH
4X C4 C5 C6 C7
1800µF
10V
VCCP
VSS
Figure 1. Pentium Pro VRM Circuit
and GND pins. At the same time, PWR GND must have a
low impedance connection to the ground plane used on
the board, as high instantaneous currents will flow in PWR
GND when N DRV L and N DRV H switch the capacitive
loads of the output MOSFET gates. A layout technique
which satisfies these requirements is to return PWR GND
to the grounded end of R1 using a high current Kelvin
connection. Figure 2 shows one successful
implementation of these PCB layout requirements.
ISENSE is an input to a medium-speed, high-sensitivity
comparator. It is often helpful to shield the trace running
from R1 to ISENSE with a “guard trace” connected to circuit
ground.
The compensation components R3 and C9 are high-
impedance nodes connected to the output of the voltage
loop error amplifier. These components should be kept in
close proximity to the ML4900. C9 should be returned to
GND, not to PWR GND or the ground plane of the PC
board. It may be helpful to shield the trace running from
R3 to COMP with a “guard trace” connected to circuit
ground.
Keep the VREF bypass capacitor C8 close to the ML4900.
Ensure that its ground connection is to GND, not PWR
GND or the ground plane of the PCB.
The VDD bypass capacitors C10 and C11 should be
returned to PWR GND or to the PC board ground plane.
They should not be returned to GND due to high transient
currents which could interfere with the current sensing
function.
In order to reduce circuit size, complexity, and cost, direct
drive of all N-channel power MOSFETs in the output stage
is employed, derived from the 12V input bus. This delivers
at least 10V of VGS enhancement to the MOSFET(s)
performing the synchronous rectification function. The
power switching MOSFET(s), however, have a worst-case
VGS enhancement of about 6V, and must therefore be
logic-level parts.
If a given design uses power MOSFETs in an 8 pin SOIC
package style, keep in mind that the thermal dissipation
capability of these parts is largely dictated by the copper
area available to their drains. A good layout will maximize
this area.
TO
ISENSE
TO
PWR GND
TO
GND
TO
SYNCHRONOUS
RECTIFIER
MOSFET
SOURCE
SENSE
RESISTOR
POWER GROUND RETURN
(GROUND PLANE)
Figure 2. Kelvin Sense Connections
7
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