AD629BNZ Просмотр технического описания (PDF) - Analog Devices
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AD629BNZ Datasheet PDF : 16 Pages
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AD629
5V/DIV
+10V
VOUT
0V
OUTPUT
ERROR
1mV = 0.01%
1mV/DIV
10µs/DIV
Figure 23. Settling Time to 0.01%, for 0 V to 10 V Output Step; G = −1, RL = 2 kΩ
350
N = 2180
300 n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
250
200
150
100
50
0
–150
–100
–50
0
50
100
150
COMMON-MODE REJECTION RATIO (ppm)
Figure 24. Typical Distribution of Common-Mode Rejection; Package Option N-8
400
350
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
300
250
200
150
100
50
0
–600
–400
–200
0
200
400
600
–1 GAIN ERROR (ppm)
Figure 25. Typical Distribution of −1 Gain Error; Package Option N-8
5V/DIV
0V
VOUT
–10V
OUTPUT
ERROR
1mV = 0.01%
1mV/DIV
10µs/DIV
Figure 26. Settling Time to 0.01% for 0 V to −10 V Output Step; G = −1, RL = 2kΩ
300
N = 2180
250 n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
200
150
100
50
0
–900 –600 –300
0
300
600
900
OFFSET VOLTAGE (µV)
Figure 27. Typical Distribution of Offset Voltage; Package Option N-8
400
350
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
300
250
200
150
100
50
0
–600
–400
–200
0
200
400
600
+1 GAIN ERROR (ppm)
Figure 28. Typical Distribution of +1 Gain Error; Package Option N-8
Rev. B | Page 8 of 16
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