HD6417708F60 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HD6417708F60

100MHz RISC CPU

Hitachi -> Renesas Electronics 

Table 1.1 SH7708 Series Features (cont)

Item

Features

Bus state

controller

(BSC)

• Supports external memory access

 32/16/8-bit external data bus

• Physical address space divided into seven areas, each a maximum 64

Mbytes, with the following features settable for each area:

 Bus size (8, 16, or 32 bits)

 Number of wait cycles (also supports a hardware wait function)

 Setting the type of space enables direct connection to DRAM,

synchronous DRAM, pseudo-SRAM, and burst ROM

 Supports fast page mode and EDO for DRAM

 Supports PCMCIA interface

 Outputs chip select signal (CS0–CS6) for corresponding area

• DRAM/synchronous DRAM/pseudo-SRAM refresh function

 Programmable refresh interval

 Supports CAS-before-RAS refresh and self-refresh modes

• DRAM/synchronous DRAM/pseudo-SRAM burst access function

• Usable as either big- or little-endian machine

Timer

• 3-channel auto-reload type 32-bit timer

• Input capture function

• 6 types of counter input clock can be selected

• Maximum resolution: 2 MHz

Realtime clock

(RTC)

• On-chip clock and calendar functions

• On-chip 32-kHz crystal oscillator circuit with a maximum resolution (interrupt

cycle) of 1/256 second

Serial communi- • Selection of asynchronous or synchronous mode

cation interface

(SCI)

• Full-duplex communication

• Supports smart card interface

Package

• 144-pin plastic QFP(FP-144)

• 144-pin plastic TQFP (TFP-144) *

Note: SH7708S only

4

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