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W83194R-58A

100MHZ AGP CLOCK FOR VIA CHIPSET

Winbond 

W83194R-58A

PRELIMINARY

8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin

Description

7

1

28 SDRAM7 (Active / Inactive)

6

1

29 SDRAM6 (Active / Inactive)

5

1

31 SDRAM5 (Active / Inactive)

4

1

32 SDRAM4 (Active / Inactive)

3

1

34 SDRAM3 (Active / Inactive)

2

1

35 SDRAM2 (Active / Inactive)

1

1

37 SDRAM1 (Active / Inactive)

0

1

38 SDRAM0 (Active / Inactive)

8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)

Bit @PowerUp Pin

Description

7

x

- Reserved

6

x

- Reserved

5

x

- Reserved

4

x

- Reserved

3

1

17 SDRAM11 (Active / Inactive)

2

1

18 SDRAM10 (Active / Inactive)

1

1

20 SDRAM9 (Active / Inactive)

0

1

21 SDRAM8 (Active / Inactive)

8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive)

Bit @PowerUp Pin

Description

7

x

- Reserved

6

x

- Reserved

5

x

- Reserved

4

1

47 AGP1 (Active / Inactive)

3

x

- Reserved

2

x

- Reserved

1

1

46 REF1 (Active / Inactive)

0

1

2 REF0 (Active / Inactive)

- 10 -

Publication Release Date: Nov. 1999

Revision 0.30

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