VG36648041CT Просмотр технического описания (PDF) - Vanguard International Semiconductor
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VG36648041CT Datasheet PDF : 70 Pages
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VIS
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
Current state
Read with auto
precharge
Write with auto
precharge
Precharging
Row activating
CS RAS CA WE Address
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op - Code
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op - code
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op - Code
H X X XX
L H H HX
L H H LX
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op - Code
Command
Action
DESL
NOP
Continue burst to end → Precharging
Continue burst to end → Precharging
BST
ILLEGAL
READ/READA ILLEGAL
WRIT/WRITA ILLEGAL
ACT
ILLEGAL
PRE/PALL
ILLEGAL
PEF/SELF
ILLEGAL
MRS
ILLEGAL
DESL
Continue burst to end → write
recovering with auto precharte
NOP
Continue burst to end → write
recovering with auto precharge
BST
ILLEGAL
READ/READA ILLEGAL
WRIT/WRITA ILLEGAL
ACT
ILLEGAL
PRE/PALL
ILLEGAL
REF/SELF
ILLEGAL
MRS
DESL
NOP
BST
ILLEGAL
Nop → Enter idle after tRP
Nop → Enter idle after tRP
Nop → Enter idle after tRP
READ/READA ILLEGAL
WRIT/WRITA ILLEGAL
ACT
ILLEGAL
PRE/PALL
Nop → Enter idle after tRP
REF/SELF
ILLEGAL
MRS
ILLEGAL
DESL
NOP
BST
Nop → Enter row active after tRCD
Nop → Enter row active after tRCD
Nop → Enter row active after tRCD
READ/READA ILLEGAL
WRIT/WRITA ILLEGAL
ACT
ILLEGAL
PRE/PALL
ILLEGAL
REF/SELF
ILLEGAL
MRS
ILLEGAL
(2/3)
Notes
11
11
3,11
3,11
11
11
3,11
3,11
3
3
3
3
3
3,9
3
Document : 1G5-0153
Rev.1
Page 11
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