UDA1350AH Просмотр технического описания (PDF) - Philips Electronics
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UDA1350AH Datasheet PDF : 36 Pages
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Philips Semiconductors
IEC 958 audio DAC
7 PINNING
SYMBOL
PIN
RESET
1
VDDD(C)
2
VSSD
3
VSSD(C)
4
L3DATA
5
L3CLOCK
6
DATAI
7
BCKI
8
WSI
9
L3MODE
10
n.c.
11
MUTE
12
SELCHAN
13
n.c.
14
SPDIF0
15
SPDIF1
16
VDDA(DAC)
17
VOUTL
18
SELCLK
19
SELSPDIF
20
LOCK
21
VOUTR
22
TC
23
Vref
24
VSSA(DAC)
25
VSSA
26
VDDA
27
n.c.
28
CLKOUT
29
PREEM1
30
VSSA(PLL)
31
VDDA(PLL)
32
BCKO
33
TEST1
34
SELSTATIC
35
DATAO
36
WSO
37
n.c.
38
TEST2
39
n.c.
40
1999 Dec 16
Preliminary specification
UDA1350AH
TYPE(1)
DISD
DS
DGND
DGND
DIOS
DIS
DISD
DISD
DISD
DIS
−
DID
DID
−
AI
AI
AS
AO
DID
DIU
DO
AO
DID
A
AGND
AGND
AS
−
DO
DO
AGND
AS
DO
DIU
DIU
DO
DO
−
DISD
−
DESCRIPTION
reset input
digital supply voltage for core
digital ground
digital ground for core
L3 interface data input and output
L3 interface clock input
I2S-bus data input
I2S-bus bit clock input
I2S-bus word select input
L3 interface mode input
not connected
mute control input
IEC 958 channel selection input
not connected
IEC 958 channel 0 input
IEC 958 channel 1 input
analog supply voltage for DAC
DAC left channel analog output
clock source for PLL selection input
IEC 958 data selection input
SPDIF and PLL lock indicator output
DAC right channel analog output
test pin; must be connected to digital ground (VSSD)
DAC reference voltage
analog ground for DAC
analog ground
analog supply voltage
not connected
clock output (256fs)
IEC 958 input pre-emphasis output 1
analog ground for PLL
analog supply voltage for PLL
I2S-bus bit clock output
test pin 1: must be connected to digital supply voltage (VDDD)
static pin control selection input
I2S-bus data output
I2S-bus word select output
not connected
test pin 2; must be connected to digital ground (VSSD)
not connected
6
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