PIN CONNECTION (Top view)
BLOCK DIAGRAM
TIMING DIAGRAM
TB62706BN/BF
Note:
Latches are level sensitive, not rising edges sensitive and not syncronus CLOCK.
Input of LATCH−terminal to H Level, data passes latches, and input to L level, data hold latches.
Input of ENABLE−terminal to H level, all output (OUT0~15) do off.
2
2006-06-14