S12MEBIV3/D Просмотр технического описания (PDF) - Freescale Semiconductor

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S12MEBIV3/D

MC9S12DT128 Device User Guide V02.09

Freescale Semiconductor 

List of Figures

MC9S12DT128 Device User Guide — V02.09

Figure 0-1 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 1-1 MC9S12DT128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 1-2 MC9S12DT128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128E, MC9S12DT128,

MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, and MC9S12DB12858

Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128E, MC9S12DG128,

MC9S12DJ128E, and MC9S12DJ128 Bondout59

Figure 2-3 Pin Assignments in 80 QFP for MC9S12DB128 Bondout . . . . . . . . . . . . . . . . . .60

Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 2-5 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 2-6 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Figure 23-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . . . .91

Figure 23-2 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128,

MC9S12DJ128E, and MC9S12DJ128) Colpitts Oscillator92

Figure 23-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .93

Figure 23-4 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128,

MC9S12DJ128E, and MC9S12DJ128) Pierce Oscillator94

Figure 23-5 Recommended PCB Layout for 80QFP (MC9S12DB128) Pierce Oscillator . . . .95

Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure A-2 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure A-3 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure A-4 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure A-5 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure A-6 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure A-7 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure A-8 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure A-9 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 23-6 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . .134

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