ML6697CH Просмотр технического описания (PDF) - Micro Linear Corporation

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ML6697CH

100BASE-TX Physical Layer with MII

Micro Linear Corporation 

ML6697

PIN DESCRIPTION (Continued)

PIN

NAME

DESCRIPTION

25

(21)

MDIO

26 (22, 23) DGND4

27 (24, 25) DVCC5

28 (26, 27) DGND5

29 (28)

PHYAD0

30 (29)

PHYAD1

31 (30)

PHYAD2

32 (31)

PHYAD3

33 (32)

PHYAD4

34 (33)

AVCC3A

35 (34)

AVCC3B

36 (35)

RGMSET

MII Management Interface data TTL input/output. Serial data are written to and read

from the ML6697’s management registers through this I/O pin. Input data is sampled

on the rising edge of MDC. Data output should be sampled synchronously with

MDC's rising edge.

Digital ground.

Digital +5V power supply.

Digital ground.

MII Serial Management Interface address bit 0.

MII Serial Management Interface address bit 1.

MII Serial Management Interface address bit 2.

MII Serial Management Interface address bit 3.

MII Serial Management Interface address bit 4.

Analog +5V power supply.

Analog +5V power supply.

Equalizer bias resistor input. An external 9.53kW, 1% resistor connected between

RGMSET and AGND3 sets internal time constants controlling the receive equalizer

transfer function.

37 (36)

38 (37, 38)

39, 40 (39, 40)

RTSET

AGND3

TPOUTN/P

Transmit level bias resistor input. An external 2.49kW, 1% resistor connected between

RTSET and AGND3 sets a precision constant bias current for the twisted pair transmit

level.

Analog ground.

Transmit twisted pair outputs. This differential current output pair drives MLT-3

waveforms into the network coupling transformer.

41 (41, 42) AGND2

Analog ground.

42 (43)

43 (44)

AVCC2

LINK100

Analog +5V power supply.

100BASE-TX link activity open-drain output. LINK100 pulls low when there is

100BASE-TX activity at TPINP/N in 100BASE-TX or auto-negotiation modes. This

output is capable of driving an LED directly.

44, 45 (45, 46)

TPINN/P

46 (47)

CMREF

52 (55)

AVCC1

Receive twisted pair inputs. This differential input pair receives 100BASE-TX signals

from the network.

Receiver common-mode reference output. This pin provides a common-mode bias

point for the twisted-pair media line receiver, typically (VCC – 1.26)V.

Analog +5V power supply.

5

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