PSB4860 Просмотр технического описания (PDF) - Siemens AG

Номер в каталоге

Компоненты Описание

Список матч

PSB4860

Digital Answering Machine with Full Duplex Speakerphone SAM EC

Siemens AG 

PSB 4860

List of Figures

Page

Figure 39: Phrase File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Miscellaneous

Figure 40: Operation Modes - State Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Interfaces

Figure 41: IOM®-2 Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 42: IOM®-2 Interface - Frame Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 43: IOM®-2 Interface - Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 44: IOM®-2 Interface - Double Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 45: SSDI Interface - Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 46: SSDI Interface - Active Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 47: SSDI Interface - Receiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 48: Analog Front End Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . 92

Figure 49: Analog Front End Interface - Frame Start . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 50: Analog Front End Interface - Data Transfer . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 51: Status Register Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 52: Data Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 53: Register Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 54: Configuration Register Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 55: Configuration Register Write Access or Register Read Command . . . . . 96

Figure 56: ARAM/DRAM Interface - Connection Diagram. . . . . . . . . . . . . . . . . . . . . 99

Figure 57: ARAM/DRAM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . 100

Figure 58: ARAM/DRAM Interface - Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . 101

Figure 59: ARAM/DRAM Interface - Refresh Cycle Timing . . . . . . . . . . . . . . . . . . . 101

Figure 60: EPROM Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 61: EPROM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 62: Flash Memory Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . 103

Figure 63: Flash Memory Interface - Multiple Devices . . . . . . . . . . . . . . . . . . . . . . 104

Figure 64: Flash Memory Interface - Command Write. . . . . . . . . . . . . . . . . . . . . . . 105

Figure 65: Flash Memory Interface - Address Write . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 66: Flash Memory Interface - Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 67: Flash Memory Interface - Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 68: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . 108

Electrical Characteristics

Figure 69: Input/Output Waveforms for AC-Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Timing Diagrams

Figure 70: Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 71: SSDI/IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . 232

Figure 72: SSDI/IOM®-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . 232

Figure 73: SSDI Interface - Strobe Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Semiconductor Group

6

10.97

Share Link: