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UAA1570HL

Global Positioning System (GPS) front-end receiver circuit

Philips Electronics 

Philips Semiconductors

Global Positioning System (GPS) front-end

receiver circuit

Product specification

UAA1570HL

SYMBOL

LIMINP

BFCP

VCCA(LIM)

DATA

VDDD

SIGN

DGND

VCCA(PLL)

SCLK

PLLGND

P39GND

PIN VOLTAGE

PIN TYPICAL VALUES (V)

DESCRIPTION

VCC = 2.7 V VCC = 5 V

29 1.696

3.999

Positive limiter input: AC couple this pin to the second IF filter

output or to ground if unused with single-ended filter

applications. The DC voltage is approximately 1 V below the

VCCA(LIM) supply on pin 31. No DC coupling.

30 1.696

3.999

Positive limiter input DC feedback loop decoupling:

AC couple this pin to ground in close proximity to the pin.

The DC voltage is approximately 1 V below the VCCA(LIM) supply

on pin 31. No DC coupling.

31 2.7

5

Limiter, sample clock squaring and sampler Emitter

Coupled Logic (ECL) circuits power supply: decouple in

close proximity to pins 26 and 31. If present, isolate from the

common VCC line sourcing the first and second mixer by placing

a large decoupling capacitor between this block and the mixers.

32 CMOS level CMOS level Serial interface data input: this DC-coupled CMOS DATA input

accepts 20-bit programming words into the synthesizer data

input register, while the STROBE is LOW, on the rising edge of

the CLOCK input. A DC short-circuit to ground is recommended

with the default frequency plan.

33 2.7

5

SIGN bit TTL output driver power supply: critically isolate and

(independent (independent separately decouple this digital VDDD supply from all other

of VCC level) of VCC level) analog (VCCA) supplies. Maintain minimum trace lengths to

decoupling components. Particular attention should be applied to

prevent coupling into VCCA(LIM) pin 31. If SAA1575HL is used,

use the digital supply from the back-end.

34 TTL output

TTL output

Amplitude and time quantized second IF output signal:

extreme care should be taken to isolate this sampled TTL output

signal from all analog traces and components, particularly the

second IF filter components at the limiter input. Avoid coupling

into the reference oscillator signal trace.

35 0

0

SIGN bit TTL output driver sink ground: critically isolate this

digital supply ground from all other analog supplies and grounds.

Maintain minimum trace lengths to decoupling components.

36 2.7

5

Synthesizer power supply: decouple in close proximity to

pin 38

37 1.34

2.5

Sample clock squaring input: accepts LOW-level AC coupled

sample clock inputs directly from the PLL reference oscillator or

DC-coupled externally squared digital clocks derived from the

PLL reference oscillator after external frequency division. The

maximum DC-coupled input level at pin 37 should not exceed

75% of the VCCA(LIM) supply value. The threshold level is set at

half the supply value on VCCA(LIM) pin 31.

38 0

0

PLL ground: minimize ground inductance; use close proximity

decoupling to the VCCA(PLL) supply pin 36

39 0

0

this pin provides additional RF/IF shielding and has to be

connected to ground

1999 May 10

8

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