MX97102 Просмотр технического описания (PDF) - Macronix International

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MX97102

ISDN S/T CONTROLLER

Macronix International 

MX97102

PIN DESCRIPTION (44-PIN)

TABLE 1: MX97102 PIN DESCRIPTIONS

LQFP PLCC

PAD# PAD# PIN NAME I/O DESCRIPTION

37

41 PAD0(D0)

Multiplexed Bus Mode:Address/data bus from the CPU system to this devic

38

42 PAD1(D1)

,and data between the CPU system and this device.

39

43 PAD2(D2)

Non-Multiplexed Bus Mode:Data bus between the CPU system and this

40

44 PAD3(D3) I/O device.

41

1

PAD4(D4)

42

2

PAD5(D5)

43

3

PAD6(D6)

44

4

PAD7(D7)

27

37 PCSN

I ChipSelect:A logic "LOW" enable this device for a read/write operation.

28

38 PWRN(R/W) I Read/Write:A logic "HIGH" indicates a valid read operation by CPU.

A logic "LOW" indicates a valid write operation by CPU.(Motorola bus

mode) Write:A logic "LOW" indicates a write operation.(Intel bus mode)

29

39 PRDN(DS) I Data Strobe:

The rising edge marks the end of a valid read or write operation (Motorola

bus mode). Read:A logic "LOW" indicates a read operation.(Intel bus mode)

8

23 PINTN

Open Interrupt Request:The signal is a logic "LOW" when this device

requests an Drain interrupt. It is an open drain output.

1~5, 14 NC

9,13,15 19,20

No used.

17~20 29,30

31~36

45~49

56,60

26

36 PALE

I Address Latch Enable:A logic "HIGH" indicates an address on the address/

data bus(Multiplexed bus type only). ALE also selects the micro-processor

interface type (multiplexed or non-multiplexed).

54

9

PRST

I/O Reset:A logic "HIGH" on this input forces this device into reset state. The

minimum pulse length is four DCL-clock periods or four ms. If the terminal

specific functions are enabled,this device may also output a reset signal.

59

13 PFSC1

O(I) Frame Sync 1:Frame sync output. Logic "HIGH" during channel 0 on the

GCI interface. This pin becomes Input if Test Mode is programmed (register

ADF1).

58

12 PDCL

O(I) Data Clock:Clock of frequency, 1536kHz output, equals to twice the GCI

data rate.

This pin becomes Input if Test Mode is programmed (register ADF1)

62

16 ECHO

O This pin output the Echo bit from the receiving line.

P/N:PM0473

REV. 2.5, SEP. 05, 2000

3

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