MC54/74HC4538A Просмотр технического описания (PDF) - Motorola => Freescale

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MC54/74HC4538A

Dual precision Monostable Multivibrator (Retriggerable, Resettable)

Motorola => Freescale 

MC54/74HC4538A

PIN DESCRIPTIONS

INPUTS

A1, A2 (Pins 4, 12)

Positive–edge trigger inputs. A rising–edge signal on

either of these pins triggers the corresponding multivibrator

when there is a high level on the B1 or B2 input.

B1, B2 (Pins 5, 11)

Negative–edge trigger inputs. A falling–edge signal on

either of these pins triggers the corresponding multivibrator

when there is a low level on the A1 or A2 input.

Reset 1, Reset 2 (Pins 3, 13)

Reset inputs (active low). When a low level is applied to

one of these pins, the Q output of the corresponding multi-

vibrator is reset to a low level and the Q output is set to a high

level.

CX1/RX1 and CX2/RX2 (Pins 2 and 14)

External timing components. These pins are tied to the

common points of the external timing resistors and capaci-

tors (see the Block Diagram). Polystyrene capacitors are

recommended for optimum pulse width control. Electrolytic

capacitors are not recommended due to high leakages

associated with these type capacitors.

GND (Pins 1 and 15)

External ground. The external timing capacitors discharge

to ground through these pins.

OUTPUTS

Q1, Q2 (Pins 6, 10)

Noninverted monostable outputs. These pins (normally

low) pulse high when the multivibrator is triggered at either

the A or the B input. The width of the pulse is determined by

the external timing components, RX and CX.

Q1, Q2 (Pins 7, 9)

Inverted monostable outputs. These pins (normally high)

pulse low when the multivibrator is triggered at either the A or

the B input. These outputs are the inverse of Q1 and Q2.

LOGIC DETAIL

(1/2 THE DEVICE)

RxCx

UPPER

REFERENCE

CIRCUIT

–

VCC

+

Vre, UPPER

OUTPUT

LATCH

M1

VCC

LOWER

REFERENCE

CIRCUIT

2 kΩ

–

M2

+

Q

M3

Vre, LOWER

Q

TRIGGER CONTROL

CIRCUIT

A

CQ

TRIGGER CONTROL

B

CB R

RESET CIRCUIT

RESET

MOTOROLA

POWER

ON

RESET

RESET LATCH

Figure 9.

3–8

High–Speed CMOS Logic Data

DL129 — Rev 6

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