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MC34115 Просмотр технического описания (PDF) - Motorola => Freescale

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MC34115 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MC34115
TYPICAL PERFORMANCE CURVES
100
70
50
30
20
10
7.0
5.0
3.0
2.0
1.0
ÇÇÇÇÇÇÇÇÇÇÇFiguÇÇÇÇÇÇÇÇÇÇÇreÇÇÇÇÇÇÇÇÇÇÇ7. TÇÇÇÇÇÇÇÇÇÇÇypicÇÇÇÇÇÇÇÇÇÇÇal IIÇÇÇÇÇÇÇÇÇÇÇnt vÇÇÇÇÇÇÇÇÇÇÇersÇÇÇÇÇÇÇÇÇÇÇusVTCIAÇÇÇÇÇÇÇÇÇÇÇGC=C=251ÇÇÇÇÇÇÇÇÇÇÇ(°2MCVeÇÇÇÇÇÇÇÇÇÇÇan±ÇÇÇÇÇÇÇÇÇÇÇ2σÇÇÇÇÇÇÇÇÇÇÇ)
Figure 8. Normalized Dynamic
Integrating Current Match versus VCC
80
TA = 25°C
60 fCLK = 16 kHz
(See Figure 6,
40 Normalized to 10 k
20 @ IGC = 1.5 mA)
0
–20
–40
–60
–80
1.0 2.0
3.0 5.0 7.0 10
20 30 50 70 100
5.0 6.0 7.0 8.0 9.0 10 11 12 13 14 15
IGC, GAIN CONTROL CURRENT (µA) – PIN 4
VCC, SUPPLY VOLTAGE (V)
Figure 9. Normalized Dynamic Integrating
Current Match versus Clock Frequency
50
25
0
–25
–50
TA = 25°C
VCC = 12 V
(See Figure 6,
–75 Normalized to 10 k
@ IGC = 1.5 mA)
–100
10
20 30 40 50 70 100
200
fCLK, CLOCK FREQUENCY (kHz)
Figure 10. Dynamic Total Loop Offset
versus Clock Frequency
1.0
0
IGC = 33 µA
–1.0
VCC = 12 V
–2.0
TA = 25°C
(See Note 3 in Electrical
Characteristics Table)
10
20 30 40 50 70 100
200
fCLK, CLOCK FREQUENCY (kHz)
Audio In
Figure 11. Block Diagram of the CVSD Encoder
Clock
ε(t)
Comparator
Sampler
Digital Out
Level Detect
Algorithm
Integrator
Slope
Polarity
Switch
Slope
Magnitude
Control
MOTOROLA ANALOG IC DEVICE DATA
7

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