CD4020B Просмотр технического описания (PDF) - Motorola => Freescale

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CD4020B

14-Bit Binary Counter

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

14-Bit Binary Counter

The MC14020B 14–stage binary counter is constructed with MOS

P–channel and N–channel enhancement mode devices in a single

monolithic structure. This part is designed with an input wave shaping circuit

and 14 stages of ripple–carry binary counter. The device advances the count

on the negative–going edge of the clock pulse. Applications include time

delay circuits, counter controls, and frequency–dividing circuits.

• Fully Static Operation

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Buffered Outputs Available from stages 1 and 4 thru 14

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ • Common Reset Line

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ • Pin–for–Pin Replacement for CD4020B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol

Parameter

Value

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD DC Supply Voltage

– 0.5 to + 18.0

V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ lin, lout Input or Output Current (DC or Transient),

± 10

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ per Pin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PD Power Dissipation, per Package†

500

mW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Tstg Storage Temperature

– 65 to + 150

_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TL

Lead Temperature (8–Second Soldering)

260

_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ * Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MC14020B

L SUFFIX

CERAMIC

CASE 620

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

ORDERING INFORMATION

MC14XXXBCP

MC14XXXBCL

MC14XXXBD

Plastic

Ceramic

SOIC

TA = – 55° to 125°C for all packages.

TRUTH TABLE

Clock

X

Reset

0

0

1

Output State

No Change

Advance to Next State

All Outputs are Low

X = Don’t Care

CLOCK

10

RESET

11

LOGIC DIAGRAM

Q1

Q4

Q5

Q12

Q13

Q14

9

7

5

1

2

3

CQ

CRQ

CQ

C RQ

CQ

C RQ

CQ

C RQ

CQ

C RQ

CQ

CR

Q6 = PIN 4

Q7 = PIN 6

Q8 = PIN 13

Q9 = PIN 12

Q10 = PIN 14

Q11 = PIN 15

VDD = PIN 16

VSS = PIN 8

REV 3

1/94

©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA

MC14020B

87

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