M65761FP Просмотр технического описания (PDF) - Renesas Electronics

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M65761FP

QM-Coder

Renesas Electronics 

M65761FP

Sequence of Setting Up Registers

(1) Initialization sequence of the internal line memory and context table RAM

This sequence starts with the initialization set up (see note) of internal line memory by the H/W RESET. It is

followed by the initialization of the context table RAM. (Clear)

1

H/W Reset

Context mode set up

Context table RAM

Initialization command issued

d7

d0

SYS_REG: 0 0 0 0 0 0 0 1

SYS_REG: 0 0 0 0 C 0 0 0

; H/W reset bit ON

; H/W reset bit OFF

; C = Context mode set up

The ON time for H/W RESET bit (The time from d0 = "1" is written

in to the time when d0 = "0" is written in) should be 100 ns more.

CMD_REG: 0 0 0 0 0 0 0 1

; Context table initialized

Interrupt enable set up

IENB_REG: 0 0 0 0 0 0 0 1

; Process end interrupt enable

[During this time, the context table RAM is initialized.]

The number of clocks needed for initialization is as follows,

When the internal text mode is used. 1024 + [clocks]

When the external text mode is used. 4096 + [clocks]

(Interrupt generation)

Set up interrupt enable

d7

d0

IENB_REG: 0 0 0 0 0 0 0 1

; Interrupt disable

Status register read out

(Check if processing finished)

STAT_REG: − − − − − − − j

; j = End of processing

j=1?

Y

N

(Error)

End of initialization command

to 2

CMD_REG: 0 0 0 0 0 0 0 0

; End of initialization

Note: Initialization of the line memory by H/W RESET is provided for the start of coding and decoding by

preparing the all white (0) data as a reference line. At the same time, it initializes the LNTP bit to

LNTP = 1 for the Typical Prediction.

REJ03F0234-0200 Rev.2.00 Sep 14, 2007

Page 17 of 33

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