M38B57MFH-XXXXFP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M38B57MFH-XXXXFP

8-BIT SINGLE-CHIP MICROCOMPUTER

MITSUBISHI ELECTRIC  

List of figures

Fig. 2.4.17 Enlarged view of FLD0 (P20) to FLD7 (P27) Tscan .............................................. 2-93

Fig. 2.4.18 Setting of relevant registers ................................................................................... 2-94

Fig. 2.4.19 FLD digit allocation example .................................................................................. 2-97

Fig. 2.4.20 Control procedure..................................................................................................... 2-98

Fig. 2.4.21 Connection diagram ............................................................................................... 2-100

Fig. 2.4.22 Timing chart of key-scan using FLD automatic display mode and digits ...... 2-101

Fig. 2.4.23 Setting of relevant registers ................................................................................. 2-102

Fig. 2.4.24 FLD digit allocation example ................................................................................ 2-105

Fig. 2.4.25 Control procedure................................................................................................... 2-106

Fig. 2.4.26 Connection diagram ............................................................................................... 2-108

Fig. 2.4.27 Timing chart of FLD display by software ........................................................... 2-108

Fig. 2.4.28 Enlarged view of P20 to P27 key-scan ................................................................ 2-108

Fig. 2.4.29 Setting of relevant registers ................................................................................. 2-109

Fig. 2.4.30 FLD digit allocation example ................................................................................ 2-110

Fig. 2.4.31 Control procedure................................................................................................... 2-111

Fig. 2.4.32 Connection diagram ............................................................................................... 2-112

Fig. 2.4.33 Timing chart of 38B5 Group and M35501FP ..................................................... 2-113

Fig. 2.4.34 Timing chart (enlarged view) of digit and segment output .............................. 2-113

Fig. 2.4.35 Setting of relevant registers ................................................................................. 2-114

Fig. 2.4.36 FLD digit allocation example ................................................................................ 2-117

Fig. 2.4.37 Control procedure................................................................................................... 2-117

Fig. 2.4.38 Connection diagram ............................................................................................... 2-118

Fig. 2.4.39 Timing chart (at correct state) of 38B5 Group and M35501FP ...................... 2-119

Fig. 2.4.40 Timing chart (at incorrect state) of 38B5 Group and M35501FP ................... 2-119

Fig. 2.4.41 Setting of relevant registers ................................................................................. 2-120

Fig. 2.4.42 Control procedure................................................................................................... 2-122

Fig. 2.5.1 Memory assignment of A-D converter relevant registers ................................... 2-125

Fig. 2.5.2 Structure of A-D control register ............................................................................ 2-125

Fig. 2.5.3 Structure of A-D conversion register (low-order) ................................................. 2-126

Fig. 2.5.4 Structure of A-D conversion register (high-order) ............................................... 2-126

Fig. 2.5.5 Structure of interrupt request register 2 ............................................................... 2-127

Fig. 2.5.6 Structure of interrupt control register 2 ................................................................ 2-128

Fig. 2.5.7 Connection diagram ................................................................................................. 2-129

Fig. 2.5.8 Setting of relevant registers ................................................................................... 2-129

Fig. 2.5.9 Control procedure ..................................................................................................... 2-130

Fig. 2.6.1 Memory assignment of PWM relevant registers .................................................. 2-132

Fig. 2.6.2 Structure of PWM register (high-order) ................................................................. 2-132

Fig. 2.6.3 Structure of PWM register (low-order) .................................................................. 2-133

Fig. 2.6.4 Structure of PWM control register ......................................................................... 2-133

Fig. 2.6.5 Connection diagram ................................................................................................. 2-134

Fig. 2.6.6 Setting of relevant registers ................................................................................... 2-134

Fig. 2.6.7 Control procedure ..................................................................................................... 2-135

Fig. 2.6.8 PWM0 output ............................................................................................................. 2-135

Fig. 2.7.1 Memory assignment of interrupt interval determination function relevant registers

...................................................................................................................................................... 2-136

Fig. 2.7.2 Structure of interrupt interval determination register........................................... 2-136

Fig. 2.7.3 Structure of interrupt interval determination control register ............................. 2-137

Fig. 2.7.4 Structure of interrupt edge selection register....................................................... 2-137

Fig. 2.7.5 Structure of interrupt request register 1 ............................................................... 2-138

Fig. 2.7.6 Structure of interrupt control register 1 ................................................................ 2-139

Fig. 2.7.7 Connection diagram ................................................................................................. 2-140

38B5 Group User’s Manual

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