LTC1427-50 Просмотр технического описания (PDF) - Linear Technology

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LTC1427-50

Micropower, 10-Bit Current Output DAC with SMBus Serial Interface

Linear Technology 

LTC1427-50

WU

W

TI I G DIAGRA S

Timing for SMBus Interface

tBUF

SDA

tHD:STA

tr

SCL

tLOW

STOP START

tHD:STA

tf

tHIGH

tHD:DAT

tSU:STA

tSU:DAT

START

tSU:STO

STOP

1427 TD01

Operating Sequence

SMBus Write Byte Protocol, with SMBus Address = 0101111B,

Command Byte = 0XXXXX11B and Data Byte = 11111111B

AD1

AD0

SMBUS ADDRESS

SDA

0 101 11 1

VCC

GND

COMMAND BYTE

VCC

GND

DATA BYTE

XXXXX 11

1 1 1 11 11 1

SCL

S

1 234

IOUT

S = START

P = STOP

* = OPTIONAL

56

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

*

P

1427 TD02

FULL-SCALE

CURRENT

ZERO-SCALE

CURRENT

APPLICATIONS INFORMATION

Digital Interface

The LTC1427-50 communicates with an SMBus host

using the standard 2-wire SMBus interface. The Timing

Diagram shows the signals on the SMBus. The SCL and

SDA bus lines must be high when the bus is not in use.

External pull-up resistors or current sources are required

at these lines.

The LTC1427-50 is a receive-only (slave) device. The

master must apply the following Write Byte protocol to

communicate with the LTC1427-50:

1

7

11

8

18

11

S Slave Address WR A Command Byte A Data Byte A P

S = Start Condition, WR = Write Bit, A = Acknowledge Bit, P = Stop Condition

The master initiates communication with the LTC1427-50

with a START condition (see SMBus Operating Sequence)

and a 7-bit address followed by the write bit = 0. The

LTC1427-50 acknowledges and the master delivers the

command byte. The LTC1427-50 acknowledges and latches

the active bits of the command byte into register A (see

Block Diagram) at the falling edge of the acknowledge

pulse. The master sends the data byte and the LTC1427-

50 acknowledges the data byte. The data byte and last two

output bits from register A are latched into register C at the

falling edge of the final acknowledge pulse and the DAC

current output assumes the new 10-bit data value (see

Block Diagram). A STOP condition is optional. The com-

6

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