LTC1427-50 Просмотр технического описания (PDF) - Linear Technology
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LTC1427-50 Datasheet PDF : 8 Pages
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LTC1427-50
PIN FUNCTIONS
SHDN (Pin 1): Shutdown. A logic low puts the chip into
shutdown mode. In shutdown, the digital settings for the
DAC are retained. On release from shutdown, the previ-
ously programmed value for IOUT is reinstated.
AD1, AD0 (Pins 2, 3): Address Selection Pins. Tie these
two pins to either VCC or GND to select one of four SMBus
addresses to which the LTC1427-50 will respond.
GND (Pin 4): Ground. Ground should be tied directly to a
ground plane.
SDA (Pin 5): SMBus Bidirectional Data Input/Digital Out-
put. This pin is an open-drain output and requires a pull-
up resistor or current source to VCC. Data is shifted into the
SDA pin and acknowledged by the SDA pin.
SCL (Pin 6): SMBus Clock Input. Data is shifted into the
SDA pin at the rising edges of the SCL clock during data
transfer.
IOUT (Pin 7): DAC Current Output.
VCC (Pin 8): Voltage Supply. This supply must be kept free
from noise and ripple by bypassing directly to the ground
plane.
FU CTIO TABLES
AD1
AD0
L
L
L
H
H
L
H
H
SMBus Address Location
0101101
0101111
0101110
0101100
DAC Power-Up Value
Zero-Scale
Zero-Scale
Zero-Scale
Midscale
Application
CCFL Backlight Control
General Purpose
General Purpose
LCD Contrast Control
BLOCK DIAGRAM
SCL
SMBUS
INTERFACE
SDA
AD0 AD1
SD
POWER-ON
RESET
SHDN
3 REGISTER A 1
3-BIT
LATCH
EN1
2
8
REGISTER B
1-BIT LATCH
EN2 SHDN
REGISTER C
10-BIT
LATCH
10
EN2
VOLTAGE
REFERENCE
SD
SD
10-BIT
CURRENT
DAC
RADJ
IOUT
1427 BD
5
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