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LT1611

Inverting 1.4MHz Switching Regulator in SOT-23

Linear Technology 

LT1611

PIN FUNCTIONS

SW (Pin 1): Switch Pin. Minimize trace area at this pin to

keep EMI down.

GND (Pin 2): Ground. Tie directly to local ground plane.

NFB (Pin 3): Negative Feedback Pin. Minimize trace area.

Reference voltage is – 1.23V. Connect resistive divider tap

here. The suggested value for R2 is 10k. Set R1 and R2

according to:

R1= VOUT − 1.23

1.23

R2

+





4.5

•

10−6

SHDN (Pin 4): Shutdown Pin. Tie to 1V or more to enable

device. Ground to shut the device down.

VIN (Pin 5): Input Supply Pin. Must be locally bypassed.

BLOCK DIAGRAM

CPL

(OPTIONAL)

VIN 5

R5

40k

Q1

VOUT

R1

(EXTERNAL)

NFB

R2

(EXTERNAL)

VIN

R6

40k

+

A1

gm

–

Q2

x10

R3

30k

R4

140k

3 NFB

RC

RAMP

GENERATOR

Σ

CC

1.4MHz

OSCILLATOR

SHDN

4

– COMPARATOR

A2

+

FF

R

Q

S

SHUTDOWN

DRIVER

A=3

1 SW

Q3

0.15Ω

2 GND

1611 BD

U

OPERATIO

Figure 2

The LT1611 combines a current mode, fixed frequency

PWM architecture with a –1.23V reference to directly

regulate negative outputs. Operation can be best under-

stood by referring to the block diagram of Figure 2. Q1 and

Q2 form a bandgap reference core whose loop is closed

around the output of the converter. The driven reference

point is the lower end of resistor R4, which normally sits

at a voltage of –1.23V. As the load current changes, the

NFB pin voltage also changes slightly, driving the output

of gm amplifier A1. Switch current is regulated directly on

a cycle-to-cycle basis by A1’s output. The flip-flop is set at

the beginning of each cycle, turning on the switch. When

the summation of a signal representing switch current and

a ramp generator (introduced to avoid subharmonic oscil-

lations at duty factors greater than 50%) exceeds the VC

signal, comparator A2 changes stage, resetting the flip-

flop and turning off the switch. Output voltage decreases

(the magnitude increases) as switch current is increased.

The output, attenuated by external resistor divider R1 and

R2, appears at the NFB pin, closing the overall loop.

Frequency compensation is provided internally by RC and

CC. Transient response can be optimized by the addition of

a phase lead capacitor, CPL, in parallel with R1 in applica-

tions where large value or low ESR output capacitors are

used.

As load current is decreased, the switch turns on for a

shorter period each cycle. If the load current is further

decreased, the converter will skip cycles to maintain

output voltage regulation.

The LT1611 can work in either of two topologies. The

simpler topology appends a capacitive level shift to a

4

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