KL5KUSB201 Просмотр технического описания (PDF) - Unspecified
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KL5KUSB201 Datasheet PDF : 21 Pages
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Kawasaki USB device
KL5KUSB201
Datasheet (digest) rev 1.1E page 15/21
8.2 Bulk OUT Transaction
Figure 8-2 shows the data timing of a Bulk OUT transaction from the host PC. When
the LSI receives OUT packet from the USB host, the LSI asserts RXACT and drives 3
bytes data received from the host. If the external SIE logic recognizes the OUT packet
is valid, it waits for the next DATA packet from USB host. If the SIE logic receives the
DATA packet correctly, it returns ACK.
Figure 8-2 Bulk OUT transaction
USB Bus (IO)
SE0 SYNC O AECep SE0
RXACT (O)
SIE_DAT[15:8] (IO)
SIE_DAT[7:0] (IO)
AE
OUT EC
SYNC D 2' 3' 4' .... n' C16ep
SE0
24
DAT 3
.... n C2
.... n-1 C1
SYNC AKep SE0
TXACT (I)
SIE_DAT[15:8] (IO)
SIE_DAT[7:0] (IO)
ACK
9. USB2.0 LSI Family
This section introduces Kawasaki’s USB2.0 LSI family.
9.1 T&MT Evaluation Daughter Card (UUT)
The daughter card which is designed based on Transceiver and Macrocell Tester
(T&MT) Interface Specification is available for evaluating the KL5KUSB201 chip.
All necesary parts including the LSI, USB connector, resistors and crystal oscillator
are attached. With using your T&MT compatible controller, the function of the LSI is
able to be evaluated such as USB2.0 Test mode function, data transfer in High Speed
or Full Speed mode and verification of functionality with the external UTMI compatible
SIE.
Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
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