IS41C16100S Просмотр технического описания (PDF) - Integrated Circuit Solution Inc

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IS41C16100S

1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Circuit Solution Inc 

IS41C16100S

IS41LV16100S

TRUTH TABLE

Function

RAS LCAS UCAS WE OE Address tR/tC I/O

Standby

Read: Word

Read: Lower Byte

H

H

H

X

X

X

High-Z

L

L

L

H

L ROW/COL DOUT

L

L

H

H

L ROW/COL Lower Byte, DOUT

Upper Byte, High-Z

Read: Upper Byte

Write: Word (Early Write)

Write: Lower Byte (Early Write)

L

H

L

H

L ROW/COL Lower Byte, High-Z

Upper Byte, DOUT

L

L

L

L

X ROW/COL DIN

L

L

H

L

X ROW/COL Lower Byte, DIN

Upper Byte, High-Z

Write: Upper Byte (Early Write)

L

H

L

L

X ROW/COL

Read-Write(1,2)

L

L

L H→L L→H ROW/COL

EDO Page-Mode Read(2) 1st Cycle: L

2nd Cycle: L

Any Cycle: L

H→L H→L H

H→L H→L H

L→H L→H H

L ROW/COL

L

NA/COL

L

NA/NA

EDO Page-Mode Write(1) 1st Cycle: L

2nd Cycle: L

H→L H→L L

H→L H→L L

X ROW/COL

X

NA/COL

EDO Page-Mode(1,2)

Read-Write

1st Cycle: L

2nd Cycle: L

H→L H→L H→L L→H ROW/COL

H→L H→L H→L L→H NA/COL

Hidden Refresh

RAS-Only Refresh

Read(2) L→H→L L

L

H

L ROW/COL

Write(1,3) L→H→L L

L

L

X ROW/COL

L

H

H

X

X

ROW/NA

CBR Refresh(4)

H→L

L

L

X

X

X

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. EARLY WRITE only.

4. At least one of the two CAS signals must be active (LCAS or UCAS).

Lower Byte, High-Z

Upper Byte, DIN

DOUT, DIN

DOUT

DOUT

DOUT

DIN

DIN

DOUT, DIN

DOUT, DIN

DOUT

DOUT

High-Z

High-Z

Integrated Circuit Solution Inc.

3

DR004-0B

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