76407D Просмотр технического описания (PDF) - Fairchild Semiconductor
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76407D Datasheet PDF : 10 Pages
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HUF76407D3, HUF76407D3S
SABER Electrical Model
REV 28 June 1999
template huf76407 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.75e-13, cjo = 5.9e-10, tt = 5.45e-8, n=1.03, m = 0.6)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 3.21e-10, is = 1e-30, m = 0.81 )
m..model mmedmod = (type=_n, vto = 2.02, kp = .83, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.39, kp = 14, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.78, kp = 0.02, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4, voff = -2.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -4)
DPLCAP
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0)
10
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -0.5)
c.ca n12 n8 = 3.9e-10
c.cb n15 n14 = 4.9e-10
c.cin n6 n8 = 3.25e-10
RSLC2
5
RSLC1
51
ISCL
RDBREAK
72
LDRAIN
DRAIN
2
RLDRAIN
RDBODY
d.dbody n7 n71 = model=dbodymod
-
50
DBREAK
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 5.42e-9
l.lsource n3 n7 = 2.57e-9
GATE
1
ESG
6
8
RDRAIN
+
EVTHRES
16
+ 19 - 21
LGATE
EVTEMP
8
RGATE + 18 - 6
9
20 22
MMED
RLGATE
MSTRO
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
CIN
8
11
MWEAK
EBREAK
+
17
18
-
7
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RSOURCE
71
DBODY
LSOURCE
SOURCE
3
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 1.06e-3, tc2 = 0
res.rdbody n71 n5 = 1.75e-2, tc1 = 1e-4, tc2 = 5e-6
res.rdbreak n72 n5 = 6.50e-1, tc1 = 1.25e-4, tc2 = 1.34e-6
res.rdrain n50 n16 = 3.7e-2, tc1 = 1.23e-2, tc2 = 2.58e-5
res.rgate n9 n20 = 3.37
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 54.2
res.rlsource n3 n7 = 25.7
res.rslc1 n5 n51 = 1e-6, tc1 = 0, tc2 =0
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.50e-2, tc1 = 1e-3, tc2 =0
res.rvtemp n18 n19 = 1, tc1 = -1.6e-3, tc2 = 1.0e-7
res.rvthres n22 n8 = 1, tc1 = -2.19e-3, tc2 = -4.97e-6
S1A
12 13
8
S2A
14
15
13
S1B
S2B
CA
13
CB
+
+ 14
EGS
6
8
-
EDS
5
8
-
RBREAK
17
18
RVTEMP
19
IT
-
VBAT
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 67.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/30))** 3))
}
}
©2001 Fairchild Semiconductor Corporation
HUF76407D3, HUF76407D3S Rev. B
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