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FS6261-01

Motherboard Clock Generator IC

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3.1 SEL_1, SEL_0

These two input pins can either tristate the output drivers,

select the Test Mode frequency, or choose the CPU fre-

quencies. Both the SEL_1 and SEL_0 pins have pull-ups

that default the CPU output frequency to either 100MHz

or 133MHz, depending on the state of the SEL_133/100#

pin. These pins should be fixed at a logic state before

power-up occurs.

3.2 SEL_133/100#

This pin is an active-low LVTTL input that switches be-

tween a 133MHz or a 100MHz system (CPU) clock. A

pull-up or pull-down must be provided externally and this

pin should be fixed at a logic state before power-up oc-

curs.

4.0 Clock Latency

All clock outputs are stopped in the low state, and are

started so that the first high pulse is a full pulse width. All

clocks complete a full period on transitions between run-

ning (enabled) and stopped (disabled) to ensure glitch-

free stop clock control.

All enabled clocks will continue to run while disabled

clocks are stopped. The clock enable signals are as-

sumed to be asynchronous inputs relative to clock out-

puts. Enable signals are synchronized to their respective

clocks by this device. The CPU and PCI clocks will tran-

sition between running and stopped according to Table 5.

4.1 Power-Up Latency

Power-up latency is defined as the time from the moment

when PWR_DWN# goes inactive (a rising edge) to when

the first valid clocks are driven from the device. Upon re-

lease of PWR_DWN#, external circuitry should allow a

minimum of 3ms for the PLLs to lock before enabling any

clocks.

4.1.1 PWR_DWN#

The PWR_DWN# signal is an asynchronous, active-low

LVTTL input that puts the device in a low power inactive

state without removing power from the device. All internal

clocks are turned off, and all clock outputs are held low.

January 2000

Powering down occurs in less than two PCI clocks from

the falling edge of PWR_DWN# to when all clock outputs

are forced low. The REF and CK48 clocks are brought

low as soon as possible.

4.2 Clock Enable Latency

Clock enable latency is defined in the number of rising

edges of free-running PCI clocks between when the en-

able signal becomes active (a rising edge) to when the

first valid clock is driven from the device.

4.2.1 CPU_STOP#

The CPU_STOP# pin is an active-low LVTTL input pin

that disables the CPU_0:3 and CK66_0:3 clocks for low

power operation. CPU_STOP# can be asserted asyn-

chronously, and the stop clock control is glitch-free, in

that the CPU clock must complete a full cycle before the

clock is stopped low. One rising edge of the PCI_F clock

is allowed before the CPU and CK66 clocks are enabled

or disabled.

4.2.2 PCI_STOP#

The PCI_STOP# pin is an active-low LVTTL input pin that

disables the PCI_1:7 clocks for low power operation, ex-

cept for the PCI_F clock. The PCI_F is a free-running

clock, and will continue to run even if all other PCI clocks

have stopped. PCI_STOP# can be asserted asynchro-

nously, and the stop-clock control is glitch-free, in that the

PCI clock must complete a full cycle before the clock is

stopped low. Only one rising edge of the PCI_F clock is

allowed after the PCI_STOP# signal is enabled/disabled.

Table 5: Latency Table

SIGNAL

SIGNAL STATE

0

CPU_STOP#

1

0

PCI_STOP#

1

0

PWR_DWN#

1

disabled

enabled

disabled

enabled

Power OFF

Power ON

PCI CLOCK ENABLE

LATENCY

1

1

1

1

2 (max.)

3ms

,62

4

1.31.00

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