FM25C160B(2014) Просмотр технического описания (PDF) - Cypress Semiconductor
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FM25C160B Datasheet PDF : 20 Pages
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FM25C160B
Status Register and Write Protection
The write protection features of the FM25C160B are multi-tiered
and are enabled through the status register. The Status Register
Table 2. Status Register
Bit 7
Bit 6
WPEN (0)
X (0)
Bit 5
X (0)
Bit 4
X (0)
is organized as follows. (The default value shipped from the
factory for bits in the Status Register is ‘0’).
Bit 3
BP1 (0)
Bit 2
BP0 (0)
Bit 1
WEL (0)
Bit 0
X (0)
Table 3. Status Register Bit Definition
Bit
Bit 0
Bit 1 (WEL)
Bit 2 (BP0)
Bit 3 (BP1)
Bit 4-6
Bit 7 (WPEN)
Definition
Description
Don’t care
This bit is non-writable and always returns ‘0’ upon read.
Write Enable Latch
WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEL = '1' --> Write enabled
WEL = '0' --> Write disabled
Block Protect bit ‘0’ Used for block protection. For details, see Table 4 on page 7.
Block Protect bit ‘1’ Used for block protection. For details, see Table 4 on page 7.
Don’t care
These bits are non-writable and always return ‘0’ upon read.
Write Protect Enable bit Used to enable the function of Write Protect Pin (WP). For details, see Table 5 on page 7.
Bits 0 and 4-6 are fixed at ‘0’; none of these bits can be modified.
Note that bit 0 (“Ready or Write in progress” bit in serial flash and
EEPROM) is unnecessary, as the F-RAM writes in real-time and
is never busy, so it reads out as a ‘0’. The BP1 and BP0 control
the software write-protection features and are nonvolatile bits.
The WEL flag indicates the state of the Write Enable Latch.
Attempting to directly write the WEL bit in the Status Register has
no effect on its state. This bit is internally set and cleared via the
WREN and WRDI commands, respectively.
BP1 and BP0 are memory block write protection bits. They
specify portions of memory that are write-protected as shown in
Table 4.
write to the Status Register. Thus the Status Register is
write-protected only when WPEN = ‘1’ and WP = ‘0’.
Table 5 summarizes the write protection conditions.
Table 5. Write Protection
WEL WPEN
WP
Protected Unprotected
Blocks
Blocks
0
X
X Protected Protected
Status
Register
Protected
1
0
X Protected Unprotected Unprotected
1
1
0 Protected Unprotected Protected
1
1
1 Protected Unprotected Unprotected
Table 4. Block Memory Write Protection
BP1
BP0
0
0
Protected Address Range
None
0
1
1
0
1
1
600h to 7FFh (upper 1/4)
400h to 7FFh (upper 1/2)
000h to 7FFh (all)
RDSR - Read Status Register
The RDSR command allows the bus master to verify the
contents of the Status Register. Reading the status register
provides information about the current state of the
write-protection features. Following the RDSR opcode, the
FM25C160B will return one byte with the contents of the Status
Register.
The BP1 and BP0 bits and the Write Enable Latch are the only
mechanisms that protect the memory from writes. The remaining
write protection features protect inadvertent changes to the block
protect bits.
The write protect enable bit (WPEN) in the Status Register
controls the effect of the hardware write protect (WP) pin. When
the WPEN bit is set to ‘0’, the status of the WP pin is ignored.
When the WPEN bit is set to ‘1’, a LOW on the WP pin inhibits a
WRSR - Write Status Register
The WRSR command allows the SPI bus master to write into the
Status Register and change the write protect configuration by
setting the WPEN, BP0 and BP1 bits as required. Before issuing
a WRSR command, the WP pin must be HIGH or inactive. Note
that on the FM25C160B, WP only prevents writing to the Status
Register, not the memory array. Before sending the WRSR
command, the user must send a WREN command to enable
writes. Executing a WRSR command is a write operation and
therefore, clears the Write Enable Latch.
Document Number: 001-86150 Rev. *A
Page 7 of 20
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