MBM30LV0032-PFTR Просмотр технического описания (PDF) - Fujitsu

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MBM30LV0032-PFTR

FLASH MEMORY CMOS 32M (4M × 8) BIT NAND-type

Fujitsu 

MBM30LV0032

s PIN DESCRIOTIONS

Pin Number Pin Name

Descriptions

18 to 21

24 to 27

I/O0 to I/O7

Data Input/Output

The I/O ports are used for transferring command, address, and input/output data

into and out of the device. The I/O pins will be high impedance when the outputs are

disabled or the device is not selected.

Command Latch Enable

2

CLE

The CLE signal enables the acquisition of the made command into the internal com-

mand register. When CLE=“H”, command are latched into the command register

from the I/O port upon the rising edge of the WE signal.

Address Latch Enable

3

ALE

The ALE signal enables the acquisition of either address or data into the internal ad-

dress/data register. The rising edge of WE latch in addresses when ALE is high and

data when ALE is low.

Chip Enable

The CE signal is used to select the device. When CE is high, the device enters a

43

CE

low power standby mode. If CE transitions high during a read operation, the standby

mode will be entered. However, the CE signal is ignored if the device is in a busy

state(R/B=L)

during a program or erase operation.

Read Enable

42

RE

The RE signal controls the serial data output. The falling edge of RE drives the data

onto the I/O bus and increments the column address counter by one.

Write Enable

4

WE

The WE signal controls writes from the I/O port. Data, address, and commands on

the I/O port are latched upon the rising of the WE pulse.

Write Protect

The WP signal protects the device against accidental erasure or programming dur-

5

WP

ing power up/down by disabling the internal high voltage generators. WP should be

kept low when the device powers up until VCC is above 2.5 V. During power down,

WP should be low when VCC falls below 2.5 V.

Spare Area Enable

40

SE

The SE input enables the spare area during sequential data input, page program,

and Read 1.

Ready Busy Output

41

R/B

The R/B output signal is used to indicate the operating status of the device. During

program, erase, or read, R/B is low and will return high upon the completion of the

operation. The output buffer for this signal is an open drain.

Output Buffer Power Supply

23

VCCq

The VCCq input supplies the power to the I/O interface logic. This power line is elec-

trically isolated from VCC for the purpose of supporting 5V tolerant I/O.

44

VCC

Power Supply

1,22

VSS

Ground

6 to 17

28 to 39

N.C. No Connection

4

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