CY62146DV30 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY62146DV30

4-Mbit (256K x 16) Static RAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle 1 (Address Transition Controlled)[16, 17]

ADDRESS

DATA OUT

tOHA

tAA

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled)[17, 18]

ADDRESS

CE

OE

BHE/BLE

tRC

tACE

tDOE

tLZOE

DATA OUT

VCC

SUPPLY

CURRENT

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

Notes:

16. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.

17. WE is HIGH for read cycle.

18. Address valid prior to or coincident with CE and BHE, BLE transition LOW.

CY62146DV30

tRC

DATA VALID

DATA VALID

tPD

tHZCE

tHZOE

tHZBE

HIGH

IMPEDANCE

ICC

50%

ISB

Document #: 38-05339 Rev. *A

Page 6 of 11

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